Displaying 11 results from an estimated 11 matches for "inc7".
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2013 Aug 16
2
[LLVMdev] [Polly] Analysis of extra compile-time overhead for simple nested loops
...d ], [ 46, %entry ]
>> %cmp314 = icmp sgt i32 %cond22, 0
>> br label %for.cond2.preheader
>> for.cond2.preheader:
>> %x.019 = phi i32 [ 0, %for.cond2.preheader.lr.ph ], [ %x.1.lcssa,
>> %for.inc6 ]
>> %a.018 = phi i32 [ 0, %for.cond2.preheader.lr.ph ], [ %inc7, %for.inc6 ]
>> br i1 %cmp314, label %for.body4, label %for.inc6
>> for.body4:
>> %x.116 = phi i32 [ %inc, %for.body4 ], [ %x.019, %for.cond2.preheader ]
>> %b.015 = phi i32 [ %inc5, %for.body4 ], [ 0, %for.cond2.preheader ]
>> %inc = add nsw i32 %x.116, 1
>...
2013 Aug 15
0
[LLVMdev] [Polly] Analysis of extra compile-time overhead for simple nested loops
...hi i32 [ %call, %cond.end ], [ 46, %entry ]
> %cmp314 = icmp sgt i32 %cond22, 0
> br label %for.cond2.preheader
> for.cond2.preheader:
> %x.019 = phi i32 [ 0, %for.cond2.preheader.lr.ph ], [ %x.1.lcssa,
> %for.inc6 ]
> %a.018 = phi i32 [ 0, %for.cond2.preheader.lr.ph ], [ %inc7, %for.inc6 ]
> br i1 %cmp314, label %for.body4, label %for.inc6
> for.body4:
> %x.116 = phi i32 [ %inc, %for.body4 ], [ %x.019, %for.cond2.preheader ]
> %b.015 = phi i32 [ %inc5, %for.body4 ], [ 0, %for.cond2.preheader ]
> %inc = add nsw i32 %x.116, 1
> %inc5 = add nsw i...
2013 Aug 16
0
[LLVMdev] [Polly] Analysis of extra compile-time overhead for simple nested loops
...>> %cmp314 = icmp sgt i32 %cond22, 0
>>> br label %for.cond2.preheader
>>> for.cond2.preheader:
>>> %x.019 = phi i32 [ 0, %for.cond2.preheader.lr.ph ], [ %x.1.lcssa,
>>> %for.inc6 ]
>>> %a.018 = phi i32 [ 0, %for.cond2.preheader.lr.ph ], [ %inc7, %for.inc6
>>> ]
>>> br i1 %cmp314, label %for.body4, label %for.inc6
>>> for.body4:
>>> %x.116 = phi i32 [ %inc, %for.body4 ], [ %x.019, %for.cond2.preheader ]
>>> %b.015 = phi i32 [ %inc5, %for.body4 ], [ 0, %for.cond2.preheader ]
>>>...
2013 Aug 15
4
[LLVMdev] [Polly] Analysis of extra compile-time overhead for simple nested loops
...hi i32 [ %call, %cond.end ], [ 46, %entry ]
%cmp314 = icmp sgt i32 %cond22, 0
br label %for.cond2.preheader
for.cond2.preheader:
%x.019 = phi i32 [ 0, %for.cond2.preheader.lr.ph ], [ %x.1.lcssa, %for.inc6 ]
%a.018 = phi i32 [ 0, %for.cond2.preheader.lr.ph ], [ %inc7, %for.inc6 ]
br i1 %cmp314, label %for.body4, label %for.inc6
for.body4:
%x.116 = phi i32 [ %inc, %for.body4 ], [ %x.019, %for.cond2.preheader ]
%b.015 = phi i32 [ %inc5, %for.body4 ], [ 0, %for.cond2.preheader ]
%inc = add nsw i32 %x.116, 1
%inc5 =...
2013 Nov 08
1
[LLVMdev] loop vectorizer and storing to uniform addresses
...%q, align 8
%inc = add nsw i64 %11, 1
store i64 %inc, i64* %q, align 8
br label %for.cond1
for.end: ; preds = %for.cond1
br label %for.inc6
for.inc6: ; preds = %for.end
%12 = load i64* %i, align 8
%inc7 = add nsw i64 %12, 1
store i64 %inc7, i64* %i, align 8
br label %for.cond
for.end8: ; preds = %for.cond
%arrayidx9 = getelementptr inbounds [4 x float]* %sum, i32 0, i64 0
%13 = load float* %arrayidx9, align 4
%arrayidx10 = getelementptr inbou...
2012 Jan 14
0
[LLVMdev] Vector ops out of loops
...r, align 4
@c = common global <2 x i16> zeroinitializer, align 4
define void @test() nounwind {
entry:
store i32 0, i32* @i, align 4
%c.promoted = load <2 x i16>* @c, align 4
br label %for.body
for.body: ; preds = %entry,
%for.body
%inc7 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
%0 = phi <2 x i16> [ %c.promoted, %entry ], [ %6, %for.body ]
%storemerge6.off0 = phi i16 [ 0, %entry ], [ %extract.t, %for.body ]
%arrayidx = getelementptr inbounds [50 x <2 x i16>]* @a, i16 0, i16
%storemerge6.off0
%1 = load &l...
2012 Dec 10
3
[LLVMdev] [PATCH] Teaching ScalarEvolution to handle IV=add(zext(trunc(IV)), Step)
...35
+ ret i32 %conv2
+}
+
+; CHECK: @kernel
+; CHECK: %add =
+; CHECK-NEXT: Exits: (9 + (zext i8 (36 + (trunc i32 %0 to i8)) to i32))
+define signext i8 @kernel() nounwind readnone {
+entry:
+ br label %for.cond1.preheader
+
+for.cond1.preheader: ; preds = %entry, %for.inc7
+ %storemerge7 = phi i32 [ 0, %entry ], [ %inc8, %for.inc7 ]
+ %0 = phi i32 [ 0, %entry ], [ %add, %for.inc7 ]
+ br label %for.body3
+
+for.body3: ; preds = %for.cond1.preheader, %for.body3
+ %storemerge15 = phi i32 [ 0, %for.cond1.preheader ], [ %inc, %fo...
2013 Nov 08
0
[LLVMdev] loop vectorizer and storing to uniform addresses
On 7 November 2013 17:18, Frank Winter <fwinter at jlab.org> wrote:
> LV: We don't allow storing to uniform addresses
>
This is triggering because it didn't recognize as a reduction variable
during the canVectorizeInstrs() but did recognize that sum[q] is loop
invariant in canVectorizeMemory().
I'm guessing the nested loop was unrolled because of the low trip-count,
and
2013 Nov 08
3
[LLVMdev] loop vectorizer and storing to uniform addresses
I am trying my luck on this global reduction kernel:
float foo( int start , int end , float * A )
{
float sum[4] = {0.,0.,0.,0.};
for (int i = start ; i < end ; ++i ) {
for (int q = 0 ; q < 4 ; ++q )
sum[q] += A[i*4+q];
}
return sum[0]+sum[1]+sum[2]+sum[3];
}
LV: Checking a loop in "foo"
LV: Found a loop: for.cond1
LV: Found an induction variable.
LV: We
2013 Aug 16
0
[LLVMdev] [Polly] Analysis of extra compile-time overhead for simple nested loops
...phi i32 [ %call, %cond.end ], [ 46, %entry ]
> %cmp314 = icmp sgt i32 %cond22, 0
> br label %for.cond2.preheader
> for.cond2.preheader:
> %x.019 = phi i32 [ 0, %for.cond2.preheader.lr.ph ], [ %x.1.lcssa, %for.inc6 ]
> %a.018 = phi i32 [ 0, %for.cond2.preheader.lr.ph ], [ %inc7, %for.inc6 ]
> br i1 %cmp314, label %for.body4, label %for.inc6
> for.body4:
> %x.116 = phi i32 [ %inc, %for.body4 ], [ %x.019, %for.cond2.preheader ]
> %b.015 = phi i32 [ %inc5, %for.body4 ], [ 0, %for.cond2.preheader ]
> %inc = add nsw i32 %x.116, 1
> %inc5 = add...
2015 Mar 05
5
[LLVMdev] RFC - Improvements to PGO profile support
> On Mar 2, 2015, at 4:19 PM, Diego Novillo <dnovillo at google.com> wrote:
>
> On Thu, Feb 26, 2015 at 6:54 PM, Diego Novillo <dnovillo at google.com <mailto:dnovillo at google.com>> wrote:
>
> I've created a few bugzilla issues with details of some of the things I'll be looking into. I'm not yet done wordsmithing the overall design document.