Displaying 4 results from an estimated 4 matches for "in8rr".
2005 Jul 11
0
[LLVMdev] X86AsmPrinter + MASM and NASM backends
...No 'intel' printers want % signs.
>
> The GAS intel code generator generates percents, look at the X86InstrInfo.td
> file it is full of them.
Ah, I see what you're talking about. Please feel free to remove all of
those from the Intel format. For example, change this:
def IN8rr : I<0xEC, RawFrm, (ops),
"in{b} {%dx, %al|%AL, %DX}">, Imp<[DX], [AL]>;
to:
def IN8rr : I<0xEC, RawFrm, (ops),
"in{b} {%dx, %al|AL, DX}">, Imp<[DX], [AL]>;
For register allocatable values, changing printOp in the
X8...
2005 Jul 12
2
[LLVMdev] X86AsmPrinter + MASM and NASM backends
>> The GAS intel code generator generates percents, look at the
>> X86InstrInfo.td file it is full of them.
>
> Ah, I see what you're talking about. Please feel free to remove all of
> those from the Intel format. For example, change this:
>
> def IN8rr : I<0xEC, RawFrm, (ops),
> "in{b} {%dx, %al|%AL, %DX}">, Imp<[DX], [AL]>;
>
> to:
>
> def IN8rr : I<0xEC, RawFrm, (ops),
> "in{b} {%dx, %al|AL, DX}">, Imp<[DX], [AL]>;
>
> For register allocatable...
2005 Jul 11
2
[LLVMdev] X86AsmPrinter + MASM and NASM backends
>>> You shouldn't have to add new classes to the .td file, just modify
>>> printOp for your asmprinters.
>>
>> I dont think printOp is virtual and therefore cannot be overriden ?
>
> Why does it need to be virtual? No 'intel' printers want % signs.
The GAS intel code generator generates percents, look at the X86InstrInfo.td
file it is full of
2005 Jul 13
0
[LLVMdev] X86AsmPrinter + MASM and NASM backends
On Tue, 12 Jul 2005, Aaron Gray wrote:
>>> X86InstrInfo.td file it is full of them.
>>
>> Ah, I see what you're talking about. Please feel free to remove all of
>> those from the Intel format. For example, change this:
>>
>> def IN8rr : I<0xEC, RawFrm, (ops),
>> "in{b} {%dx, %al|%AL, %DX}">, Imp<[DX], [AL]>;
>>
>> to:
>>
>> def IN8rr : I<0xEC, RawFrm, (ops),
>> "in{b} {%dx, %al|AL, DX}">, Imp<[DX], [AL]>;
>>...