Displaying 6 results from an estimated 6 matches for "in64bitmod".
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in64bitmode
2018 Mar 28
1
Taking over an x86 opcode for my own instruction
....
In this case, I used 0xF1, and created the following instruction:
def CACHE_OPERAND_B64i : RIi64<0xF1, AddRegFrm, (outs GR64:$unused),
(ins i64imm:$b), "cache_operand_b_i64\t$b",
[(int_cache_operand_b_i64 i64imm:$b)]>,
Requires<[In64BitMode]>;
However, when I compile, I'm getting errors of the form:
Error: Primary decode conflict: TEST64ri32 would overwrite
CACHE_OPERAND_B64i
ModRM 199
Opcode 247
Context IC_64BIT_REXW
When I look at the definition of TEST64ri32, I see:
let Predicates = [In64BitMode] in
def TEST64ri32 :...
2011 Sep 30
2
[LLVMdev] LLVM backends instruction selection
I am new to the LLVM backends, I am wondering how instruction selection is
done in LLVM backends, I looked at the .td files in Target/X86, they all
seem to be small and do not deal with common X86 instructions, i.e. mov,
push, pop, etc.
Thanks
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2015 Jul 02
2
[LLVMdev] [x86] Compiling in 32-bit mode causes 64-bit asm source to be silently converted to its 32-bit equavilent
Hi Craig,
I am Charles Li from Sony Playstation.
We are doing x86 code gen testing and, by chance, we noticed that compiling the 64-bit assembly instruction<https://msdn.microsoft.com/en-us/library/windows/hardware/ff561499(v=vs.85).aspx> "jrcxz" in 32-bit mode "-m32"
previously resulted in an error,
now gets silently converted into the 32-bit equivalent instruction
2011 Oct 16
0
[LLVMdev] Problem with X86Subtarget::IsLegalToCallImmediateAddr()
The current rule is:
/// IsLegalToCallImmediateAddr - Return true if the subtarget allows calls
/// to immediate address.
bool X86Subtarget::IsLegalToCallImmediateAddr(const TargetMachine &TM) const {
if (In64BitMode)
return false;
return isTargetELF() || TM.getRelocationModel() == Reloc::Static;
}
But this is not doing the correct thing for ELF PIC. The
straight-forward way to fix this is to change the || to &&.
However, this would make the function always return false for other
object file fo...
2018 Mar 01
0
[X86] API to query MCInstr operand types
...nsion.td)
def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src),
"movs{lq|xd}\t{$src, $dst|$dst, $src}",
[(set GR64:$dst, (sextloadi64i32 addr:$src))],
IIC_MOVSX>,
Sched<[WriteALULd]>, Requires<[In64BitMode]>;
Given an MCInstrDesc object, I'd like to know of a way to find out the type
of 'ins' operand i32mem.
I am particularly interested in figuring out the type of a memory operand
of a given MCInstrDesc, if one exists.
Thanks for any help,
Bharadwaj
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2018 Aug 06
2
Lowering ISD::TRUNCATE
I'm working on defining the instructions and implementing the lowering
code for a Z80 backend. For now, the backend supports only the native
CPU-supported datatypes, which are 8 and 16 bits wide (i.e. no 32 bit
long, float, ... yet).
So far, a lot of the simple stuff like immediate loads and return values
is very straightforward, but now I got stuck with ISD::TRUNCATE, as in: