Displaying 6 results from an estimated 6 matches for "imuldiv".
2011 Aug 15
2
[LLVMdev] Question on instruction itineraries
...of all, is there a document that describes the instruction itinerary
model in some detail ?
For example looking at MBlaze target MBlaeSchedule.td I can see something
like
MblazeSchedule.td
...
def IIImul : InstrItinClass;
...
InstrItinData<IIImul , [InstrStage<17, [IMULDIV]>]>,
Does that mean Mul's are expected to have a latency of 17 clks ? Mips target
has something similar.
In Mblaze case I can see the result being used the very next cycle
mul *r3*, r6, r5
addik r3,* r3*, 4
similarly for my target (instead of 17 I'm speci...
2011 Aug 16
0
[LLVMdev] Question on instruction itineraries
...ibes the instruction itinerary
> model in some detail ?
> For example looking at MBlaze target MBlaeSchedule.td I can see something
> like
> MblazeSchedule.td
> ...
> def IIImul : InstrItinClass;
> ...
> InstrItinData<IIImul , [InstrStage<17, [IMULDIV]>]>,
>
> Does that mean Mul's are expected to have a latency of 17 clks ? Mips target
> has something similar.
Yes.
> In Mblaze case I can see the result being used the very next cycle
> mul r3, r6, r5
> addik r3, r3, 4
> similarly for my t...
2011 Aug 17
1
[LLVMdev] Question on instruction itineraries
...model in some detail ?
> > For example looking at MBlaze target MBlaeSchedule.td I can see something
> > like
> > MblazeSchedule.td
> > ...
> > def IIImul : InstrItinClass;
> > ...
> > InstrItinData<IIImul , [InstrStage<17, [IMULDIV]>]>,
> >
> > Does that mean Mul's are expected to have a latency of 17 clks ? Mips
> target
> > has something similar.
>
> Yes.
>
> > In Mblaze case I can see the result being used the very next cycle
> > mul r3, r6, r5
> >...
2013 Sep 25
1
[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
...eflects the real R4xxx/R5xxx processors.
>
> why IILoad uses funcition unit ALU?
> InstrItinData<IILoad , [InstrStage<3, [ALU]>]>
>
>
This means IILoad instructions use resource ALU for three cycles. I don't
remember why only two functional units (ALU and IMULDIV) are defined and
used in this .td file, but this would be incorrect if load instructions did
not have any resource conflicts with other ALU instructions on your target.
>
> for my previous question, I have new input after reading the code.
> pre-RA-sched is derived from ScheduleDAGSNodes...
2013 Sep 20
0
[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
Hi, Akira,
I found you maintain mips MipsSchedule.td. does it correct? in
MipsSchedule.td, every InstrItinData only uses one InstrStage. there's no
ByPass info out there.
are you sure this reflects the real R4xxx/R5xxx processors.
why IILoad uses funcition unit ALU?
InstrItinData<IILoad , [InstrStage<3, [ALU]>]>
for my previous question, I have new input after
2013 Sep 20
2
[LLVMdev] Does Mips resolve hazard in pre-ra-sched or post-ra-sched?
Akira,
Thanks you for response.
I understand Post-RA schedule make uses of scoreboardHazardRecognizer. But
I found mips codes are good enough by default. basically, I can not easily
eyeball any bubbles.
I don't understand how they can do that without post-RA-sched.
pre-ra-scheduler eg. (SelectionDAG/ScheduleDAGRRList.cpp) has little
information and they can only schedule node in topology