Displaying 2 results from an estimated 2 matches for "imul64rr".
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imul64rm
2020 May 12
2
BPF tablegen+codegen question
...does tablegen+codegen ensure that dst and src2 are the same register? I
see that the assembly/disassembly string assumes this is the case.
Also, it uses i64:$src which is an i64 and not a GPR. What is the
distinction there? X86 does this differently. src1 and src2 are GR64
registers.
def IMUL64rr : RI<0xAF, MRMSrcReg, (outs GR64:$dst),
(ins GR64:$src1, GR64:$src2),
"imul{q}\t{$src2, $dst|$dst, $src2}",
[(set GR64:$dst, EFLAGS,
(X86smul_flag GR64:$src1, GR64:$src2))]>,...
2008 Jul 30
2
[LLVMdev] Really nasty remat bug [LONG]
...tuff added by me so you won't get the same output with upstream
llvm -debug).
#####
There's a sequence of instructions that looks like this before linear scan:
#####
2800 %reg1591<def> = SUB64rr %reg1591, %reg1589, %EFLAGS<imp-def,dead> ;
srcLine 0
2808 %reg1591<def> = IMUL64rr %reg1591, %reg1055, %EFLAGS<imp-def,dead> ;
srcLine 0
2816 %reg1591<def> = ADD64rr %reg1591, %reg1579, %EFLAGS<imp-def,dead> ;
srcLine 0
2820 %reg1198<def> = LEA64r %reg1591, 1, %reg1574, 0 ; srcLine 0
#####
%reg1591 gets spilled by linear scan with all of the uses in...