Displaying 6 results from an estimated 6 matches for "imul32rr".
2018 Nov 14
2
Fw: How to define an instruction
...:
Hi,
I have some questions about instructions again.
I have add a DAG successfully,I think.Because what I do can be compiled to LLVM IR and binary file.
I guess, the schedule of an instruction tells the machine how to do . I don't konw if it's right.
For example,there is the definition of IMUL32rr in X86InstrArithmetic.td. "WriteIMul32Reg" is the most important and the defines the multiplication.
def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),"imul{l}\t{$src2, $dst|$dst, $src2}", [(set GR32:$dst, EFLAGS, (X86smul_flag GR32:$src1, GR32...
2018 Nov 14
2
Fw: How to define an instruction
...:
Hi,
I have some questions about instructions again.
I have add a DAG successfully,I think.Because what I do can be compiled to LLVM IR and binary file.
I guess, the schedule of an instruction tells the machine how to do . I don't konw if it's right.
For example,there is the definition of IMUL32rr in X86InstrArithmetic.td. "WriteIMul32Reg" is the most important and the defines the multiplication.
def IMUL32rr : I<0xAF, MRMSrcReg, (outs GR32:$dst), (ins GR32:$src1,GR32:$src2),"imul{l}\t{$src2, $dst|$dst, $src2}", [(set GR32:$dst, EFLAGS, (X86smul_flag GR32:$src1, GR32...
2010 Sep 01
1
[LLVMdev] equivalent IR, different asm
On Sep 1, 2010, at 11:14 AM, Dale Johannesen wrote:
>
> On Sep 1, 2010, at 6:25 AMPDT, Argyrios Kyrtzidis wrote:
>
>> The attached .ll files seem equivalent, but the resulting asm from
>> 'opt-fail.ll' causes a crash to webkit.
>> I suspect the usage of registers is wrong, can someone take a look ?
>
> Yes, the code here is wrong:
>
>> movl
2006 Jun 26
2
[LLVMdev] Mapping bytecode to X86
...%reg1024 = MOV32rm <fi#-2>, 1, %NOREG, 0
%reg1025 = MOV32rm %reg1024, 1, %NOREG, 0
%reg1026 = MOVSX32rm8 %reg1025, 1, %NOREG, 0
%reg1027 = MOVSX32rm8 %reg1025, 1, %NOREG, 1
ADJCALLSTACKDOWN 8
%reg1028 = ADD32rr %reg1026, %reg1027
%reg1029 = IMUL32rr %reg1028, %reg1027
MOV32mr %ESP, 1, %NOREG, 4, %reg1029
MOV32mi %ESP, 1, %NOREG, 0, <ga:.str_1>
CALLpcrel32 <ga:printf>
ADJCALLSTACKUP 8, 0
%reg1030 = MOV32rr %EAX
%reg1031 = IMPLICIT_DEF_GR32
%EAX = MOV32rr %reg1031
RET
M...
2018 Nov 07
2
how to add a instruction
...et GR32:$dst,(X86max_qb GR32:$src1, GR32:$src2))]>,Sched<[WriteIMul16Reg]>,OpSize32 ;
when compile LLVM , the error appears.
"[ 97%] Updating X86GenAsmWriter1.inc...
Unhandled immediate encoding GR32
Unhandled immediate encoding
"
But when I write the same as the instruction IMUL32rr, there is no error in compiling.(I don't use the EFLAGS at all, so I think it's wrong. Indeed, it made a error when using it.)
let Defs = [EFLAGS] in {
let Constraints = "$src1 = $dst" in {
let isCommutable = 1 in {
def max_qb : I<0xF0,MRMSrcReg, (outs GR32:$dst), (ins GR32:$s...
2014 Dec 22
2
[LLVMdev] Marking implicit registers as "trashed"
I am working on some optimizations for our VLIW processor; one ALU performs
32-bit operations, while another performs 8-, 16- or 32-bit operations.
Sometimes it is useful for the 32-bit ALU to perform 8- or 16-bit operations
such as ADD, SUB, SHL, AND, etc. that are not dependent on the additional
24-bits, but because it is 32-bit ALU, the condition codes are updated.
When this is being used to