Displaying 6 results from an estimated 6 matches for "implicitdefin".
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implicitdefine
2009 May 13
2
[LLVMdev] RFC: Code Gen Change!
...made these
changes.
Instead of all of the booleans, you pass in a flag that has bits set
to indicate what state the register is in:
namespace RegState {
enum {
Define = 0x1,
Implicit = 0x2,
Kill = 0x4,
Dead = 0x8,
EarlyClobber = 0x10,
ImplicitDefine = Implicit | Define,
ImplicitKill = Implicit | Kill
};
}
class MachineInstrBuilder {
MachineInstr *MI;
public:
explicit MachineInstrBuilder(MachineInstr *mi) : MI(mi) {}
/// addReg - Add a new virtual register operand...
///
const
MachineInstrBuilder &addReg(unsigned RegN...
2009 May 13
0
[LLVMdev] RFC: Code Gen Change!
...e booleans, you pass in a flag that has bits set
> to indicate what state the register is in:
>
> namespace RegState {
> enum {
> Define = 0x1,
> Implicit = 0x2,
> Kill = 0x4,
> Dead = 0x8,
> EarlyClobber = 0x10,
> ImplicitDefine = Implicit | Define,
> ImplicitKill = Implicit | Kill
> };
> }
[...]
> MachineInstrBuilder &addReg(unsigned RegNo, unsigned flags = 0,
> unsigned SubReg = 0) const {
Hi Bill,
I definitely like this change. The staccato bool arguments are
i...
2015 Jul 29
0
[LLVMdev] [3.7.0] Two late issues with cross compilation to mips
...d() calls isn't always 2*PI.
According to -print-after-all, the pass that moves the instruction is Simple Register Coalescing. The bit I'm stuck on at the moment is that I'm not sure what information is supposed to prevent this move from happening. I thought there was supposed to be an ImplicitDefine on the call instruction for each clobbered register but this doesn't seem to be the case. Am I missing something obvious?
________________________________________
From: Daniel Sanders
Sent: 29 July 2015 11:08
To: Hans Wennborg (hans at chromium.org)
Cc: Simon Atanasyan (simon at atanasyan.com)...
2015 Jul 30
2
[LLVMdev] [3.7.0] Two late issues with cross compilation to mips
...isn't always 2*PI.
>
> According to -print-after-all, the pass that moves the instruction is Simple Register Coalescing. The bit I'm stuck on at the moment is that I'm not sure what information is supposed to prevent this move from happening. I thought there was supposed to be an ImplicitDefine on the call instruction for each clobbered register but this doesn't seem to be the case. Am I missing something obvious?
> ________________________________________
> From: Daniel Sanders
> Sent: 29 July 2015 11:08
> To: Hans Wennborg (hans at chromium.org <mailto:hans at chromi...
2015 Jul 30
0
[LLVMdev] [3.7.0] Two late issues with cross compilation to mips
...d() calls isn't always 2*PI.
According to -print-after-all, the pass that moves the instruction is Simple Register Coalescing. The bit I'm stuck on at the moment is that I'm not sure what information is supposed to prevent this move from happening. I thought there was supposed to be an ImplicitDefine on the call instruction for each clobbered register but this doesn't seem to be the case. Am I missing something obvious?
________________________________________
From: Daniel Sanders
Sent: 29 July 2015 11:08
To: Hans Wennborg (hans at chromium.org<mailto:hans at chromium.org>)
Cc: Simon...
2015 Jul 29
5
[LLVMdev] [3.7.0] Two late issues with cross compilation to mips
Hi,
Sorry for the late report but I've only just found these issues. Llvm.org isn't working for me at the moment but I'll file tickets once it is.
The issues are:
1. Almabench has some significant numerical differences and fails the reference check for some configs. I'm investigating this one at the moment but early indications are that it's a similar (but different)