Displaying 3 results from an estimated 3 matches for "implicit_def_gr32".
2006 Jun 26
2
[LLVMdev] Mapping bytecode to X86
...reg1028 = ADD32rr %reg1026, %reg1027
%reg1029 = IMUL32rr %reg1028, %reg1027
MOV32mr %ESP, 1, %NOREG, 4, %reg1029
MOV32mi %ESP, 1, %NOREG, 0, <ga:.str_1>
CALLpcrel32 <ga:printf>
ADJCALLSTACKUP 8, 0
%reg1030 = MOV32rr %EAX
%reg1031 = IMPLICIT_DEF_GR32
%EAX = MOV32rr %reg1031
RET
My allocator produces this mapping:
FNSTCW16m :=
MOV8mi :=
FLDCW16m :=
MOV32rm EAX :=
MOV32rm EAX := EAX
MOVSX32rm8 ECX := EAX
MOVSX32rm8 EAX := EAX
ADJCALLSTACKDOWN...
2008 Feb 04
0
[LLVMdev] Exception handling in JIT
...m!\n");
> case TargetInstrInfo::LABEL:
> - assert(0 && "JIT does not support meta labels!\n");
> + MCE.emitLabel(MI.getOperand(0).getImm());
> + break;
> case X86::IMPLICIT_DEF_GR8:
> case X86::IMPLICIT_DEF_GR16:
> case X86::IMPLICIT_DEF_GR32:
> @@ -613,7 +622,6 @@
> case X86::IMPLICIT_DEF_VR128:
> case X86::FP_REG_KILL:
> break;
> -#endif
> case X86::MOVPC32r: {
> // This emits the "call" portion of this pseudo instruction.
> MCE.emitByte(BaseOpcode);
> @@ -627,7 +635,6...
2008 Feb 01
2
[LLVMdev] Exception handling in JIT
Dear all,
Here's a new patch with Evan's comments (thx Evan!) and some cleanups.
Now the (duplicated) exception handling code is in a new file:
lib/ExecutionEngine/JIT/JITDwarfEmitter.
This patch should work on linux/x86 and linux/ppc (tested).
Nicolas
-------------- next part --------------
An embedded and charset-unspecified text was scrubbed...
Name: jit-exceptions.patch
URL: