search for: impliciations

...PUs flag register: The scheduler has to respect the order! We are interested in liveness, but we do not necessarily want to spill/reload them or perform register allocation on a single register. - X87 floating point stack registers need special handling on top of the generic register allocation == Impliciations == Except for the register allocator not using them they behave like normal registers: - We track the liveness of unallocatable registers - The scheduler respects data/output dependencies for unallocatable registers == Examples == Assume r0 is a normal register, r1 is an unallocatable register (bu...

...duler has to respect the order! We are interested in liveness, but we do not necessarily want to spill/reload them or perform register allocation on a single register. >> - X87 floating point stack registers need special handling on top of the generic register allocation >> >> == Impliciations == >> Except for the register allocator not using them they behave like normal registers: >> - We track the liveness of unallocatable registers >> - The scheduler respects data/output dependencies for unallocatable registers >> >> == Examples == >> Assume r0 is...

...er: The scheduler has to respect the order! We are interested in liveness, but we do not necessarily want to spill/reload them or perform register allocation on a single register. > - X87 floating point stack registers need special handling on top of the generic register allocation > > == Impliciations == > Except for the register allocator not using them they behave like normal registers: > - We track the liveness of unallocatable registers > - The scheduler respects data/output dependencies for unallocatable registers > > == Examples == > Assume r0 is a normal register, r1 is...

...er: The scheduler has to respect the order! We are interested in liveness, but we do not necessarily want to spill/reload them or perform register allocation on a single register. > - X87 floating point stack registers need special handling on top of the generic register allocation > > == Impliciations == > Except for the register allocator not using them they behave like normal registers: > - We track the liveness of unallocatable registers > - The scheduler respects data/output dependencies for unallocatable registers > > == Examples == > Assume r0 is a normal register, r1 is...

...respect the order! We are interested in liveness, but we do not necessarily want to spill/reload them or perform register allocation on a single register. >>> - X87 floating point stack registers need special handling on top of the generic register allocation >>> >>> == Impliciations == >>> Except for the register allocator not using them they behave like normal registers: >>> - We track the liveness of unallocatable registers >>> - The scheduler respects data/output dependencies for unallocatable registers >>> >>> == Examples == &g...

...PUs flag register: The scheduler has to respect the order! We are interested in liveness, but we do not necessarily want to spill/reload them or perform register allocation on a single register. - X87 floating point stack registers need special handling on top of the generic register allocation == Impliciations == Except for the register allocator not using them they behave like normal registers: - We track the liveness of unallocatable registers - The scheduler respects data/output dependencies for unallocatable registers == Examples == Assume r0 is a normal register, r1 is an unallocatable register (bu...

On 02/25/2016 06:14 PM, Matthias Braun via llvm-dev wrote: > 1) The value read from a reserved register cannot be predicted. Reading a reserved register twice may each time produce a different result. This seems broken to me that treating another copy should be assumed to produce a different result. This seems like it should be optimized, and have a special volatile_copy instruction for the

...duler has to respect the order! We are interested in liveness, but we do not necessarily want to spill/reload them or perform register allocation on a single register. >> - X87 floating point stack registers need special handling on top of the generic register allocation >> >> == Impliciations == >> Except for the register allocator not using them they behave like normal registers: >> - We track the liveness of unallocatable registers >> - The scheduler respects data/output dependencies for unallocatable registers >> >> == Examples == >> Assume r0 is...

...er: The scheduler has to respect the order! We are interested in liveness, but we do not necessarily want to spill/reload them or perform register allocation on a single register. > - X87 floating point stack registers need special handling on top of the generic register allocation > > == Impliciations == > Except for the register allocator not using them they behave like normal registers: > - We track the liveness of unallocatable registers > - The scheduler respects data/output dependencies for unallocatable registers > > == Examples == > Assume r0 is a normal register, r1 is...

Ok, I think we've done enough damage for one release. Thanks everyone for pulling a long weekend to get changes prepared and reviewed. We're still missing the threaded input stuff, but that needs more review and I think we wore Tiago out this time around. If someone wants to propose merging it after the freeze, I think we should consider doing it. Note that this tarball depends on