search for: immzext16

...oundary condition where k==-32768 Then it creates the literal -32769 which cannot be placed in a simple immediate field. That creates a lot of extra code for Mips 16. I had originally written a pattern for setge when the right operand is a constant. def: Mips16Pat <(setge CPU16Regs:$lhs, immZExt16:$rhs), (XorRxRxRy16 (SltiCCRxImmX16 CPU16Regs:$lhs, immZExt16:$rhs), (LiRxImmX16 1))>; I was able to work around this boundary case by doing the reverse transformation at the boundary. i..e. z = (x > (k-1)) => z = (x >= k) def: Mips16Pat <(setgt CPU16Regs:$lhs, -3276...

...Another good example is the PPC backend, which has the exact same issue > for integer constants. Actually, for SPU, not quite the same: def ILHU : RI16Form<0b010000010, (ops GPRC:$rT, u16imm:$val), "ilhu $rT, $val", LoadNOP, [(set GPRC:$rT, immZExt16:$val)]>; def IOHL : RI16Form<0b100000110, (ops GPRC:$rT, u16imm:$val), "iohl $rT, $val", LoadNOP, [(set GPRC:$rT, immZExt16:$val)]>; Thus, you can't really do as the PPC does, viz: (ORI (LIS (HI16 imm:$imm)), (LO16 imm:$imm)) vs...

On Tue, 9 Jan 2007, Evan Cheng wrote: >> - How does one deal with multiple instruction sequences in a pattern? >> To load a constant is a two instruction sequence, but both >> instructions only take two operands (assume that r3 is a 32-bit >> register): >> >> ilhu $3, 45 # r3 = (45 << 16) >> iohl $3, 5 # r3 |= 5

..."addui", add, simm16, immSExt16>; However sticky speaking this should be in dlx the instructions are addui rk, ri, Kuns (Where Kusn is unsigned) Likewise DLX has a subui rk, ri, Kusn. (Mips does not) Thus they should be: def ADDui : ArithI<0x09, "addui", add, simm16, immZExt16>; def SUBui : ArithI<0x23, "subui", sub, simm16, immZExt16>; However I am not sure how or where to setup in the Target Descriptor of the Instructions or (even the .cpp) to get it to support 16-bit sign constants that that are negative to map to the SUBui. Doing the above chan...

...hich has the exact same >> issue >> for integer constants. > > Actually, for SPU, not quite the same: > > def ILHU : RI16Form<0b010000010, (ops GPRC:$rT, u16imm:$val), > "ilhu $rT, $val", LoadNOP, > [(set GPRC:$rT, immZExt16:$val)]>; > > def IOHL : RI16Form<0b100000110, (ops GPRC:$rT, u16imm:$val), > "iohl $rT, $val", LoadNOP, > [(set GPRC:$rT, immZExt16:$val)]>; > > Thus, you can't really do as the PPC does, viz: > > (ORI (LIS (...

There can also be other “problems" like this one: http://reviews.llvm.org/D6946 <http://reviews.llvm.org/D6946> - Matthias > On Apr 20, 2015, at 1:44 PM, Tim Northover <t.p.northover at gmail.com> wrote: > >> The DAG combiner also performs the undefined shift -> undef though, so it >> should still be OK > > DAG combiner doesn't really run to

...------------------------------===// // Arbitrary patterns that map to one or more instructions //===----------------------------------------------------------------------===// // Small immediates def : MipsPat<(i32 immSExt16:$in), (ADDiu ZERO, imm:$in)>; def : MipsPat<(i32 immZExt16:$in), (ORi ZERO, imm:$in)>; def : MipsPat<(i32 immLow16Zero:$in), (LUi (HI16 imm:$in))>; Here are some which have several instructions multiclass SetgePats<RegisterClass RC, Instruction SLTOp, Instruction SLTuOp> { def : MipsPat<(setge RC:$lhs,...

Thanks for your reply. We are trying to implement a simple Mips-based CPU with just for teaching purpose, so we delete some instructions which are not commonly used, thus the task won't be too hard for students. I am responsible for modifying the compiler so that the compiler won't emit unsupported instructions. In order to avoid "can not select" error, I am trying to expand