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...64-s0:64:64-f80:128:128" target triple = "x86_64-unknown-linux-gnu" @gpregs = common global [32 x i32] zeroinitializer, align 4 ; <[32 x i32]*> [#uses=2] define void @"instr_direct_rri$op_addi$imm16$"() nounwind { entry: %tmp = tail call i16 @llvm.immread.i16.i32(i32 2) nounwind ; <i16> [#uses=1] %shr = sext i16 %tmp to i32 ; <i32> [#uses=1] %tmp10 = load i32* getelementptr ([32 x i32]* @gpregs, i32 0, i64 28) ; <i32> [#uses=1] %add = add i32 %tmp10, %shr ; <...

Hi Adam, > One problem, I was trying to solve was, that I need to declare variables of let's say 5-bit width like 'i5 var', > the maximal bit-width may be limited to 64 bits. I need such variables to represent instruction's operands, > example is at the end this message. any standard compliant C compiler supports i5, believe it or not. Try this: #include

Hi Adam, John is right, the TCE stuff would be useful for you. Our compiler targets a processor template that the designer can populate pretty freely. The compiler then reads the architecture description and creates an LLVM backend on the fly. Please don't hesitate to get in touch with us if you have questions. -- Pertti

Hello gyus, I am working on a project, where we are trying to create a development environment for new ASIP processor design. Part of this project is a compiler generator, where we would like to generate C compiler from some instruction description. To keep it short, let's say, that in each instruction's semantics is described by some C code. What I would like to do is to compile this