search for: immod

...>; >> >> multiclass ABD_NonCommutative<string asmstr, SDPatternOperator OpNode, >> RegisterClass srcAReg, RegisterClass srcBReg, >> RegisterClass dstReg, ValueType srcAType, ValueType >> srcBType, ValueType dstType, >> Operand ImmOd, ImmLeaf imm_type> >> { >> .... >> def IMM_MEM_MEM : SetABDIn<asmstr, ImmOd, memhx, memhx, >> [(directStore (dstType (OpNode >> imm_type:$srcA, (srcBType (load addr16:$srcB)))), addr16:$dstD)]>; >> .......

...s, GPRRegs, DSTRegs, i16, i16, i16, simm16, immZExt16x>; multiclass ABD_NonCommutative<string asmstr, SDPatternOperator OpNode, RegisterClass srcAReg, RegisterClass srcBReg, RegisterClass dstReg, ValueType srcAType, ValueType srcBType, ValueType dstType, Operand ImmOd, ImmLeaf imm_type> { .... def IMM_MEM_MEM : SetABDIn<asmstr, ImmOd, memhx, memhx, [(directStore (dstType (OpNode imm_type:$srcA, (srcBType (load addr16:$srcB)))), addr16:$dstD)]>; ..... } class SetABDIn<string asmstr, DAGOperand srcA,...

Here is the instruction in question: multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass srcAReg, RegisterClass dstReg, ValueType srcAType, ValueType dstType, Operand ImmOd, ImmLeaf imm_type> { def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, [(set dstReg:$dstD, (OpNode srcAReg:$srcA))]>; def IMM_REG : SetADInOut<asmstr, ImmOd, dstReg, [(set dstReg:$dstD, (OpNode imm_type:$srcA))]>;...

...AM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Here is the instruction in question: > > multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass > srcAReg, > RegisterClass dstReg, ValueType srcAType, > ValueType dstType, Operand ImmOd, ImmLeaf imm_type> > { > def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, > [(set dstReg:$dstD, (OpNode > srcAReg:$srcA))]>; > def IMM_REG : SetADInOut<asmstr, ImmOd, dstReg, > [(set dstReg:$dstD, (...

Thanks for your reply. We are propagating sign info to tablegen currently using BinaryWithFlagsSDNode.Flags.hasNoSignedWrap atm. I imagine (I have not looked) they are printed according to instruction in AsmPrinter.cpp (pure speculation). I'm still confused as to why 0x7FFF is ok to match 16 bit int but not 0x8000? Thanks. On Wed, Feb 15, 2017 at 1:44 PM, Manuel Jacob <me at

...3 at gmail.com> wrote: >> >> Here is the instruction in question: >> >> multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass >> srcAReg, >> RegisterClass dstReg, ValueType srcAType, >> ValueType dstType, Operand ImmOd, ImmLeaf imm_type> >> { >> def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, >> [(set dstReg:$dstD, (OpNode >> srcAReg:$srcA))]>; >> def IMM_REG : SetADInOut<asmstr, ImmOd, dstReg, >>...

...t;>> >>> Here is the instruction in question: >>> >>> multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass >>> srcAReg, >>> RegisterClass dstReg, ValueType srcAType, >>> ValueType dstType, Operand ImmOd, ImmLeaf imm_type> >>> { >>> def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, >>> [(set dstReg:$dstD, (OpNode >>> srcAReg:$srcA))]>; >>> def IMM_REG : SetADInOut<asmstr, ImmOd, dstReg, >>>...

...gt; Here is the instruction in question: >>>> >>>> multiclass AD<string asmstr, SDPatternOperator OpNode, RegisterClass >>>> srcAReg, >>>> RegisterClass dstReg, ValueType srcAType, >>>> ValueType dstType, Operand ImmOd, ImmLeaf imm_type> >>>> { >>>> def REG_REG : SetADInOut<asmstr, srcAReg, dstReg, >>>> [(set dstReg:$dstD, (OpNode >>>> srcAReg:$srcA))]>; >>>> def IMM_REG : SetADInOut<asmstr, ImmOd, dstR...

Hi Ryan, > On Aug 24, 2015, at 6:49 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > > Quentin, > > I apologize for the spamming here but in getVR (where VReg is assigned an RC), it calls: > > const TargetRegisterClass *RC = TLI->getRegClassFor(Op.getSimpleValueType()); > VReg = MRI->createVirtualRegister(RC); > > My question is why is it using the