search for: immleaf

...def simm16 : Operand<i16> { let DecoderMethod= "DecodeSimm16"; let OperandType = "OPERAND_IMMEDIATE"; } def uimm16 : Operand<i16> { let PrintMethod = "printUnsignedImm"; let OperandType = "OPERAND_IMMEDIATE"; } def immSExt16x : ImmLeaf<i16, [{ return isInt<16>(Imm); }]>; def immZExt16x : ImmLeaf<i16, [{ return isUInt<16>(Imm); }]>; defm SUB16u_ : ABD_NonCommutative<"sub16u", unsignedSub, LOADRegs, GPRRegs, DSTRegs, i16, i16, i16, simm16, immZExt16x>; multiclass ABD_NonCommutative<stri...

...ot;; >> let OperandType = "OPERAND_IMMEDIATE"; >> } >> >> def uimm16 : Operand<i16> { >> let PrintMethod = "printUnsignedImm"; >> let OperandType = "OPERAND_IMMEDIATE"; >> } >> >> def immSExt16x : ImmLeaf<i16, [{ return isInt<16>(Imm); }]>; >> def immZExt16x : ImmLeaf<i16, [{ return isUInt<16>(Imm); }]>; >> >> defm SUB16u_ : ABD_NonCommutative<"sub16u", unsignedSub, LOADRegs, >> GPRRegs, DSTRegs, i16, i16, i16, simm16, immZExt16x>; &g...

...uot;, "pc"), 0x00, 0xA6, [] > { let Inst{31-24} = offset{7-0}; let Inst{23-16} = offset{15-8}; let Inst{15} = 0b1; let Inst{14-13} = 0b00; let Inst{12-8} = 0b01101; let Inst{7-0} = opcode; } and I have def pcoffset8 : Operand<i8>, ImmLeaf<i8, [{ return Immediate >= -128 && Immediate <= 127; }]> { let PrintMethod = "printPCRelImmOperand"; let MIOperandInfo = (ops i8imm); let ParserMatchClass = ImmediateAsmOperand<"Imm8">; let EncoderMethod = "getMemOpValue"; let Decode...

Hi, I am trying to make my tablegen files more flexible and for that I would like to have a name that in the end will be replaced with a type. If tablegen would support c preprocssing, I would do it like this: --- #define myBaseType i32 ... def imm32 : Operand<myBaseType>; def immZExt10 : ImmLeaf<myBaseType, [{return isUInt<10>(Imm);}]>; ... --- Is there a way to achieve something like this with tablegen ? Greetings, Jeroen Dobbelaere

Hmm, I'm getting nowhere pretty fast. It seems 68000 with its CISC nature is quite complex to implement for a novice. I can see how to implement simple stuff, like -- move dn, dn move dn, (an) As that just turns into stores, sets, etc. But how would you represent things like indexed access? move dn, (an,dn) move dn, offset(an) Can I only really define very simple operations for the main

Hi all, I'm trying to get GlobalISel up and running on an off-tree architecture and am thinking I must be doing something wrong, given by how few things actually work. Namely, any ImmLeaf pattern will fail to match if there is a (TRUNC/ZEXT/SEXT) applied to the constant operand, all of which are commonly created through Legalization. This is due to G_CONSTANT being explicitly looked for by the tablegened code, rather than code that makes use of getConstantVRegVal. Is there supposed...

...looking directly for G_CONSTANT. That's not as easy as you make it sound :-) but let's suppose we can recognize enough of the underlying pattern to be able to use getConstantVRegVal() instead of needing to do a direct translation of the SelectionDAG pattern. In the SelectionDAG patterns an ImmLeaf is an `imm` node with arbitrary C++ predicate(s) attached. There's no practical way to programatically fold a sext/zext/trunc node into the arbitrary C++ code to allow it to match a plain G_CONSTANT, as well as a zexted/sexted/trunced G_CONSTANT. For example, `isUInt<16>(Imm)` will fail i...

Ok, this makes sense. So, my follow up is then why, as in Mips, R600, etc... the bit value is checked in the tablegen. Seems that we should expect it to fit anyways if it still exists at this point? I'm having a hard time trying to get shl to take a PatLeaf for Imm instead of an ImmLeaf. On Mon, Apr 20, 2015 at 4:11 PM, David Majnemer <david.majnemer at gmail.com> wrote: > > > On Mon, Apr 20, 2015 at 1:00 PM, Ryan Taylor <ryta1203 at gmail.com> wrote: > >> For example: >> >> unsigned int x, y; >> >> void foo() >> { >...

Hello, I'm trying to define in my new back end, in MyBackendInstrInfo.td file, a vector load instruction that takes an immediate address operand. (I got inspired from Mips' MSA SIMD extensions.) Could you please tell me what's the right way to do it? Here, the load class has $addrsrc which is a relative address with base a certain register and offset: class

...re flexible and for that I would like > to have a name that in the end will be replaced with a type. > > If tablegen would support c preprocssing, I would do it like this: > > --- > #define myBaseType i32 > ... > def imm32 : Operand<myBaseType>; > def immZExt10 : ImmLeaf<myBaseType, [{return isUInt<10>(Imm);}]>; ... > --- > > Is there a way to achieve something like this with tablegen ? > > Greetings, > > Jeroen Dobbelaere > > > > > > _______________________________________________ > LLVM Developers mail...

Hi, I'm trying to use predicated TImmLeafs in TableGen patterns with GlobalISel to select intrinsics with immediate operands. While this is working so far, contrary to ImmLeafs the predicate does not seem to get checked. Is this not supported yet? This is the pattern in question: def tuimm9 : TImmLeaf<i32, [{ return isUInt<9>...

...Note that in the end I managed to fix this problem by using an address operand as immediate operand (inspired again from Mips MSA vector instructions), but I consider this a somewhat strange solution: class REP_1R_DESC_BASE<Operand MemOpnd = uimm4_ptr, ImmLeaf Addr = immLeaf, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs); dag InOperandList = (ins MemOpnd:$addrdst); string AsmString = "REPEAT_X_TIMES($addrdst );"; list<dag> Pattern = [(int_c...

...etc. Note however that my vector unit has a separate memory space. This is why I defined the vector store like: class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode, ValueType TyNode, RegisterOperand ROWD, Operand MemOpnd = uimm4_ptr, ImmLeaf Addr = immLeafAlex, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs); dag InOperandList = (ins ROWD:$wd, MemOpnd:$addrdst); string AsmString = !strconcat("LS[$addrdst] = $wd;", instr_asm);...

Thanks for your reply. We are propagating sign info to tablegen currently using BinaryWithFlagsSDNode.Flags.hasNoSignedWrap atm. I imagine (I have not looked) they are printed according to instruction in AsmPrinter.cpp (pure speculation). I'm still confused as to why 0x7FFF is ok to match 16 bit int but not 0x8000? Thanks. On Wed, Feb 15, 2017 at 1:44 PM, Manuel Jacob <me at

Hi Peter, I would recommend looking into the implementation of the matcher if you want to add more builtin types: utils/TableGen//DAGISelMatcherGen.cpp That being said, you can define your own types without having to go through that hassle. E.g., from AArch64 def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> { let ParserMatchClass = SImm9Operand; } Wouldn’t that work for you? Cheers, -Quentin > On May 25, 2016, at 5:06 PM, Lawrence, Peter via llvm-dev <llvm-dev at lists.llvm.org> wrote: > > Dumb question about llvm-tb...

...lgen Hi Peter, I would recommend looking into the implementation of the matcher if you want to add more builtin types: utils/TableGen//DAGISelMatcherGen.cpp That being said, you can define your own types without having to go through that hassle. E.g., from AArch64 def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> { let ParserMatchClass = SImm9Operand; } Wouldn’t that work for you? Cheers, -Quentin On May 25, 2016, at 5:06 PM, Lawrence, Peter via llvm-dev <llvm-dev at lists.llvm.org<mailto:llvm-dev at lists.llvm.org>> wrote:...

Dumb question about llvm-tblgen for "XyzGenInstrInfo.inc" If I have a pattern in my dot-td-file like this [(set i32:$dst (add i32:$rs1, i32:$rs2))] The question is where does the token "i32" come from, I don't see any definitions for i1, i8, i16, i32, ... in include/llvm/Target/*.td while I do see definitions for tokens like

...etc. Note however that my vector unit has a separate memory space. This is why I defined the vector store like: class ST_DESC_BASE<string instr_asm, SDPatternOperator OpNode, ValueType TyNode, RegisterOperand ROWD, Operand MemOpnd = uimm4_ptr, ImmLeaf Addr = immLeafAlex, InstrItinClass itin = NoItinerary> { dag OutOperandList = (outs); dag InOperandList = (ins ROWD:$wd, MemOpnd:$addrdst); string AsmString = !strconcat("LS[$addrdst] = $wd;", instr_asm);...

...'t see any mention of predicates in lang ref manual. A DAG should have an operator, one or more return value and a bunch of arguments. Each of them would have a type. I am not sure how that maps to syntax provided by TableGen language. In TargetSelectionDAG.td I see (vt SDNode) in definition of ImmLeaf. Does that mean vt is return type of SDNode? 2. Entity followed after "(" is always need to be an operator? or it can be ValueType or something else? 3. What are keywords like "ins", "outs" and "ops"? They are not mentioned in lang ref manual either. 4. Wha...

...ecommend looking into the implementation of the matcher if you want to add more builtin types: > utils/TableGen//DAGISelMatcherGen.cpp > > That being said, you can define your own types without having to go through that hassle. > E.g., from AArch64 > def simm9 : Operand<i64>, ImmLeaf<i64, [{ return Imm >= -256 && Imm < 256; }]> { > let ParserMatchClass = SImm9Operand; > } > > Wouldn’t that work for you? > > Cheers, > -Quentin > > > On May 25, 2016, at 5:06 PM, Lawrence, Peter via llvm-dev <llvm-dev at lists.llvm.org &...