search for: immediantly

On Dec 27, 2017 2:00 PM, "Matt Arsenault" <arsenm2 at gmail.com> wrote: > On Dec 26, 2017, at 18:42, Sean Silva via llvm-dev < llvm-dev at lists.llvm.org> wrote: > > Thanks! That looks like a winning approach. > > I swear I grepped around for ISD::Constant but for some reason never found this code. I think maybe I was searching for ISD::Constant with

Hi Kevin, To get some portion of a constant immediate you can use SDNodeXForms to transform constant SDNodes into other values. For a worked example, in the MIPS backend we use this for constant synthesis by materializing the value into a register: (From lib/Target/MipsInstrInfo.td): // Transformation Function - get the lower 16 bits. def LO16 : SDNodeXForm<imm, [{ return getImm(N,

Hi all, This seems like a dumb question but while setting up a pattern in TD file, I got stuck on trying to get each half of an immediate as the half-sized type (ie. i64 imm -> pair of i32 imm's). Is there an existing way to do it? I've tried the 'EXTRACT_SUBREG' but that seems to error at the end of scheduling. Looking at Target.td, I'm not sure which opcode is meant

Hi, I'm doing a backend port and I'm having trouble with adds that have negative immediates. My architecture only has instructions for subtracting and adding 8bit immediate values (they will be zero-extended, thus unsigned). Bigger immediates have to be moved in a register first. The problem is: Expressions like "b - 1" result in "add nsw i32 %b, -1" in LLVM IR. They

Hi everyone, The WebAssembly backend recently had Bug 39448 <https://bugs.llvm.org/show_bug.cgi?id=39448> filed against it because NaN payloads in floating-point immediates are not preserved through compilation on 32-bit builds. I took a look and the corruption takes place when the immediates are converted from APFloats to be stored as native doubles in MCOperand. I assume this bug only

I have a question about inserting instructions into the LLVM IR. I can insert instructions, but my operands do not have the right type, so it fails an assertion at runtime. I am trying to insert an immediate load instructions, as a means of claiming a new register. Here is what I do: Builder.SetInsertPoint(LLVMBB, I); // The following line looks to me like it would have a chance of loading

Hello, the hot key assigned to a MENU BEGIN (via MENU LABEL) doesn't cause the submenu to be entered automatically when MENU IMMEDIATE is used (at previous level). Here's a patch over syslinux 6.03. Patch was tested on Debian. Regards Dany *Sample config* # hot keys: S,1,2 are immediate (screen flash), but not E MENU IMMEDIATE LABEL standard MENU LABEL ^Standard MENU BEGIN MENU LABEL

I'm trying to add intrinsics for the Signal Processing Engine (FPU/vector unit) on some PowerPC cores, but running into a problem. Some of the instructions take an immediate operand, but I can't figure out how to make the intrinsic use an immediate, it just wants to load a register as an argument to the function. Is there any way in the .td file to describe the intrinsic as taking an

When I''m executing cucumber tests, I noticed that sometimes rails app (in test env.) getting several the same requests (GET or POST) usually around 3, and it doesn''t render anything with empty HTTP status code. Have anyone met something similar to that issue? here is some example of log file: Started POST "/account" for 127.0.0.1 at 2010-11-30 22:34:17 +0200

Hello, Im (trying) to write a backend for a simple 32bit processor architecture, with a single instruction format having no condition code registers. www.docm.mmu.ac.uk/STAFF/A.Nisbet/Sabre.pdf is the short 15 page document describing the architecture of Sabre. It is a Celoxica developed research/teaching processor, pages 5-8 contain relevant information for targetting it from a new compiler

Hello, I want to use withCallingHandlers(expr, warning = function(w) { ....}), that is, to use a custom warning handler. I want this handler to replicate the behavior of the usual handler. I have problems with the mode 'options(warn = 0)' where the warnings are delayed, except if calling 'warning("message", immediate. = TRUE). Indeed, if my custom warning handler

I currently have two channel groups in my zapata.conf file. I would like one group to be immediate=yes and the other immediate=no Does not seem to matter which way I go, the first entry in overrides my explicit setting for the second group. I am running * 1.0.9 on FC1 [trunkgroups] ;trunkgroup => 1,24 trunkgroup => 1,48,72 ;spanmap => 1,1,0 spanmap => 2,1,0 spanmap => 3,1,1

When using a channel bank for analog handsets, you have a couple options in the way you handle transactions involving the analog handsets and origination. With immediate set to no, it appears to me that soon as a digit is pressed after going off-hook, the single digit is taken and processed against the context that the channel is associated with from the configuration in zapata.conf. With

Ivan, Sorry, no, I wasn't clear enough. Both "op dst_reg,immediate,src_reg" and "op dst_reg,src_reg,immediate" are allowed in the ALU ops. For most instructions these are two different things - e.g. sub a,5,b is different from sub,a,b,5 obviously - but for things like add they just define the same thing. My problem is that LLVM won't allow immediates on the LHS of

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I was trying to do a pattern matching for a rd+imm instruction in my own backend. It looks something like: def: Pat<build_vector v2i16:$src1, v2i16:$src2, (OR (SLLI GPR: $src1,16), GPR:$src2>; OR takes two i32 in registers and SLLI takes one i32 in registers and an immediate. But the immediate '16' does not work here and I tried different ways. May I know if any of you have any idea

Hi, I'm using asterisk 1.2.7.1 and somehow my iax trunking is getting these problem :S. Sometimes iax acts weird and start to drop calls randomly and give these at the log: May 16 13:44:22 DEBUG[5264] chan_iax2.c: Immediately destroying 6, having received INVAL May 16 13:44:22 DEBUG[5264] chan_iax2.c: Immediately destroying 6, having received INVAL May 16 13:44:22 DEBUG[5264]

This commit adds support for dadd with an immediate src in gk110 code. The machine-code in question is generated by e.g. nouveau_compiler with the new "Make use of double immediates" patch series when building the piglit glsl-algebraic-double-add.shader_test. This commit changes the output from: 00000010: 001c0001 c38001ff $r0 $r0 $r0 $r0 0x3fe00 0x3fe00 0x3fe0000000000000

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When immediate is set on a port that is an fxo, what is the meaning of this ? Will it go immediately to the "s" extension of the context when the line first rings, or something else ? I am looking for a way to stop the line ringing two extra times before being answered by the channel bank. (caller id is set to off I believe, and the lines in question don't have it anyway.)