search for: ilp

Hi, I am currently writing a paper documenting a research project that we have done on pre-allocation instruction scheduling to balance ILP and register pressure. In the paper we compare the pre-allocation scheduler that we have developed to LLVM's default schedulers for two targets: x86-64 and x86-32. We would like to include in our paper some brief descriptions of the two LLVM schedulers that we are comparing against and some...

On Sep 17, 2011, at 10:07 AM, Ghassan Shobaki wrote: > Hi, > > I am currently writing a paper documenting a research project that we have done on pre-allocation instruction scheduling to balance ILP and register pressure. In the paper we compare the pre-allocation scheduler that we have developed to LLVM's default schedulers for two targets: x86-64 and x86-32. We would like to include in our paper some brief descriptions of the two LLVM schedulers that we are comparing against and some inf...

Hi Andrew, What we have is not a patch to any of LLVM's schedulers. We have implemented our own scheduler and integrated it into LLVM 2.9 as yet-another scheduler. Our scheduler uses a combinatorial optimization approach to balance ILP and register pressure. In one experiment, we added more precise latency information for most common x86 instructions to our scheduler and noticed a 10% performance improvement on one FP2006 benchmark, namely gromacs. More precisely, we compared: (1) LLVM2.9+ourScheduler+preciseLatency against...

...p 23, 2011, at 6:16 AM, Ghassan Shobaki wrote: > Hi Andrew, > > What we have is not a patch to any of LLVM's schedulers. We have implemented our own scheduler and integrated it into LLVM 2.9 as yet-another scheduler. Our scheduler uses a combinatorial optimization approach to balance ILP and register pressure. In one experiment, we added more precise latency information for most common x86 instructions to our scheduler and noticed a 10% performance improvement on one FP2006 benchmark, namely gromacs. More precisely, we compared: > > (1) LLVM2.9+ourScheduler+preciseLatency &...

...tion will help us better document and analyze the results of our benchmark tests that compare our algorithm with LLVM's pre-allocation scheduling algorithm. First, here is a brief description of our work: We have developed a combinatorial algorithm for balancing instruction-level parallelism (ILP) and register pressure (RP) during pre-allocation scheduling. The algorithm is based on a branch-and-bound (B&B) approach, wherein the objective function is a linear combination of schedule length and register pressure. We have implemented this algorithm and integrated it into LLVM 2.9 as an al...

...Sep 23, 2011, at 6:16 AM, Ghassan Shobaki wrote: Hi Andrew, > > >What we have is not a patch to any of LLVM's schedulers. We have implemented our own scheduler and integrated it into LLVM 2.9 as yet-another scheduler. Our scheduler uses a combinatorial optimization approach to balance ILP and register pressure. In one experiment, we added more precise latency information for most common x86 instructions to our scheduler and noticed a 10% performance improvement on one FP2006 benchmark, namely gromacs. More precisely, we compared: > > >(1) LLVM2.9+ourScheduler+preciseLatency...

...tter document and analyze the results of our benchmark tests that compare our algorithm with LLVM's pre-allocation scheduling algorithm. > > First, here is a brief description of our work: > > We have developed a combinatorial algorithm for balancing instruction-level parallelism (ILP) and register pressure (RP) during pre-allocation scheduling. The algorithm is based on a branch-and-bound (B&B) approach, wherein the objective function is a linear combination of schedule length and register pressure. We have implemented this algorithm and integrated it into LLVM 2.9 as an al...

...generate the best PPC schedules, there is one thing you may > >> want to override. The scheduler's priority function has a > >> HasReadyFilter attribute (enum). It can be overriden by specializing > >> hybrid_ls_rr_sort. Setting this to "true" enables proper ILP > >> scheduling, and maximizes the instructions that can issue in one > >> group, regardless of register pressure. We still care about register > >> pressure enough in ARM to avoid enabling this. I'm really not sure how > >> much it will help on modern PPC im...

On 17.09.2013, at 20:04, Ghassan Shobaki <ghassan_shobaki at yahoo.com> wrote: > Hi Andy, > > We have done some experimental evaluation of the different schedulers in LLVM 3.3 (source, BURR, ILP, fast, MI). The evaluation was done on x86-64 using SPEC CPU2006. We have measured both the amount of spill code as well as the execution time as detailed below. > > Here are our main findings: > > 1. The SD schedulers significantly impact the spill counts and the execution times for...

...h noting that 39.1 GFLOP/s is approaching the theoretical limits of the processor (stated to be 45.25 GFLOP/s single-precision). I've used the llc utility to test various pre-register-allocation instruction schedulers with the following results: -pre-RA-sched =default - discards ILP =list-burr - discards ILP =list-tdrr - crashes during code generation =source - preserves interleaved instruction ordering and ILP =list-hybrid - discards ILP =list-ilp - discards ILP =list-td - crashes during code generation =fa...

...the best PPC schedules, there is one thing you may >>>> want to override. The scheduler's priority function has a >>>> HasReadyFilter attribute (enum). It can be overriden by specializing >>>> hybrid_ls_rr_sort. Setting this to "true" enables proper ILP >>>> scheduling, and maximizes the instructions that can issue in one >>>> group, regardless of register pressure. We still care about register >>>> pressure enough in ARM to avoid enabling this. I'm really not sure how >>>> much it will help on m...

...the PLDI paper: Balancing Register Allocation Across Threads for a Multithreaded Network Processor Xiaotong Zhuang and Santosh Pande PLDI'04 Another take (and quite not a longshot although probably Fernando -- thanks for the debugger, will try it -- has worked either alone or with NVK on the ILP formulation) is to write-up constraints for an ILP (integer linear programming) solution. I wouldn't mind to wait forever (for several minutes that is ^_^) for a valid register allocation to complete. My application programs range between 50 (the smallest) to about 2K instructions. Basic blocks...

...ument and analyze the results of our benchmark tests that compare our > algorithm with LLVM's pre-allocation scheduling algorithm. > > First, here is a brief description of our work: > > We have developed a combinatorial algorithm for balancing instruction-level > parallelism (ILP) and register pressure (RP) during pre-allocation scheduling. > The algorithm is based on a branch-and-bound (B&B) approach, wherein the > objective function is a linear combination of schedule length and register > pressure. We have implemented this algorithm and integrated it into LL...

Dear guys, does any one of you have an ILP register allocator implemented in LLVM and would be willing to give it to me, so I can compare with my algorithm? Actually, if you could cite a paper where an ILP algorithm is used (in LLVM), at least I would be able to look at the numbers. Preferebly, it would have to be for x86. Thanks a lot...

...Hz with 24 GB of memory. Each CPU has 8 threads (16 threads in total). All our tests, however, were single threaded. Which result is particularly surprising for you? The low impact of the MI scheduler, the relatively good performance of the source scheduler or the relatively poor performance of the ILP scheduler? Thanks -Ghassan  ________________________________ From: Benjamin Kramer <benny.kra at gmail.com> To: Ghassan Shobaki <ghassan_shobaki at yahoo.com> Cc: Andrew Trick <atrick at apple.com>; "llvmdev at cs.uiuc.edu" <llvmdev at cs.uiuc.edu> Sent: Thu...

> > Another take (and quite not a longshot although probably Fernando -- thanks for > the debugger, will try it -- has worked either alone or with NVK on the ILP > formulation) is to write-up constraints for an ILP (integer linear programming) > solution. I wouldn't mind to wait forever (for several minutes that is ^_^) for > a valid register allocation to complete. My application programs range between > 50 (the smallest) to about 2K instru...

...ndrew Trick wrote: Now, to generate the best PPC schedules, there is one thing you may > want to override. The scheduler's priority function has a > HasReadyFilter attribute (enum). It can be overriden by specializing > hybrid_ls_rr_sort. Setting this to "true" enables proper ILP > scheduling, and maximizes the instructions that can issue in one > group, regardless of register pressure. We still care about register > pressure enough in ARM to avoid enabling this. I'm really not sure how > much it will help on modern PPC implementations though. > hybrid_ls...

...: > Now, to generate the best PPC schedules, there is one thing you may >> want to override. The scheduler's priority function has a >> HasReadyFilter attribute (enum). It can be overriden by specializing >> hybrid_ls_rr_sort. Setting this to "true" enables proper ILP >> scheduling, and maximizes the instructions that can issue in one >> group, regardless of register pressure. We still care about register >> pressure enough in ARM to avoid enabling this. I'm really not sure how >> much it will help on modern PPC implementations though...

Hi Andy, We have done some experimental evaluation of the different schedulers in LLVM 3.3 (source, BURR, ILP, fast, MI). The evaluation was done on x86-64 using SPEC CPU2006. We have measured both the amount of spill code as well as the execution time as detailed below. Here are our main findings: 1. The SD schedulers significantly impact the spill counts and the execution times for many benchmarks, but...

By using analyze -stats -instcounts <bytecode> I can get the total number of instructions but I want to extract instruction level parallelism . That is I want to know number of add instruction that can be executed in parallel, similarly for multiply ... This would give me an idea what is upper limit of adders ( and multipliers )should be there in my hardware. Any kind of help would be