Displaying 3 results from an estimated 3 matches for "il_op_uav_add".
2010 Nov 08
2
[LLVMdev] Creating tablegen patterns for intrinsics with no return value.
...TIL_BinAtomNoRet : SDTypeProfile<0, 3, [
SDTCisPtrTy<0>, SDTCisVT<1, i32>, SDTCisVT<2, i32>
]>;
Node:
def atom_g_add_noret : SDNode<"AMDILISD::ATOM_G_ADD_NORET", SDTIL_BinAtomNoRet, [SDNPHasChain]>;
Pattern:
def ATOM_G_ADD_NORET : BinAtomNoRet<IL_OP_UAV_ADD,
"_id($id)", atom_g_add_noret>;
I am Lowering INTRINSIC_W_CHAIN to lower from @llvm.amdil.atomic.add.gi32.noret to the correct instruction with the following code sequence.
LowerINTRINSIC_W_CHAIN(...)
{
...
case AMDILIntrinsic::AMDIL_atomic_add_gu32_noret:
IntNo =...
2010 Nov 08
0
[LLVMdev] Creating tablegen patterns for intrinsics with no return value.
...pattern should suffice to tell the compiler that there's more going on than it can detect just by looking at the inputs and outputs, and so it won't delete the instruction. Something like the following should do the trick:
let hasSideEffects = 1 in
def ATOM_G_ADD_NORET : BinAtomNoRet<IL_OP_UAV_ADD,
"_id($id)", atom_g_add_noret>;
For an existing example, have a look at the memory barrier instruction definitions for the ARM target (DMB and DMB_MCR in ARMInstrInfo.td).
Regards,
Jim
>
> Here is my profile/node/pattern.
> Profile:
> def SDTIL_BinAtomNoRet : S...
2010 Nov 08
1
[LLVMdev] Creating tablegen patterns for intrinsics with no return value.
...tell the compiler that there's more going on than it can
> detect just by looking at the inputs and outputs, and so it won't
> delete the instruction. Something like the following should do the
> trick:
> let hasSideEffects = 1 in
> def ATOM_G_ADD_NORET : BinAtomNoRet<IL_OP_UAV_ADD,
> "_id($id)", atom_g_add_noret>;
>
> For an existing example, have a look at the memory barrier instruction
> definitions for the ARM target (DMB and DMB_MCR in ARMInstrInfo.td).
>
> Regards,
> Jim
[Villmow, Micah] Jim, Thanks for the hint, but I tried t...