search for: iit_v128

...long lanemask. But now I get the following error when giving make llc: <<error:unhandled vector type width in intrinsic!>> This error comes from this file https://github.com/llvm-mirror/llvm/blob/master/utils/TableGen/IntrinsicEmitter.cpp, comes from the fact there is no IIT_V128 (nor IIT_V256), and they is a switch case using them in method static void EncodeFixedType(Record *R, std::vector<unsigned char> &ArgCodes, std::vector<unsigned char> &Sig). Is there any reason these enum IIT_Info ( IIT_V128, IIT_V256) are not added in file /IntrinsicEmitte...

...SIMD units with more than 32 lanes (32 >> subregisters per vector >> register) in TableGen, llc and opt. For example, I use SIMD >> instructions with types >> v128i16 and v512i16. >> >> An important questions I have is if it is OK to add the types >> IIT_V128 = 37, IIT_V256 >> = 38 like I did below: >> enum IIT_Info { >> ... >> IIT_V2 = 9, >> IIT_V4 = 10, >> IIT_V8 = 11, >> IIT_V16 = 12, >> IIT_V32 = 13, >> ... >...

...rote: > Hello. > I managed to use SIMD units with more than 32 lanes (32 subregisters per vector > register) in TableGen, llc and opt. For example, I use SIMD instructions with types > v128i16 and v512i16. > > An important questions I have is if it is OK to add the types IIT_V128 = 37, IIT_V256 > = 38 like I did below: > enum IIT_Info { > ... > IIT_V2 = 9, > IIT_V4 = 10, > IIT_V8 = 11, > IIT_V16 = 12, > IIT_V32 = 13, > ... > IIT_V64 = 16, >...

Hello. In my TableGen back end description I need to use more than 32 (e.g., 128, 1024, etc) subregisters per register for my research SIMD processor. I have used so far with success 32 subregisters. However, when using 128 subregisters when I now give the command: llvm-tblgen -gen-register-info Connex.td I get an error message "error:Ran out of lanemask bits to