Displaying 4 results from an estimated 4 matches for "iit_info".
2017 Jul 28
2
Addressing TableGen's error "Ran out of lanemask bits" in order to use more than 32 subregisters per register
...gt; register) in TableGen, llc and opt. For example, I use SIMD
>> instructions with types
>> v128i16 and v512i16.
>>
>> An important questions I have is if it is OK to add the types
>> IIT_V128 = 37, IIT_V256
>> = 38 like I did below:
>> enum IIT_Info {
>> ...
>> IIT_V2 = 9,
>> IIT_V4 = 10,
>> IIT_V8 = 11,
>> IIT_V16 = 12,
>> IIT_V32 = 13,
>> ...
>> IIT_V64 = 16,
>> IIT_V1 = 28,
>>...
2017 Jul 28
0
Addressing TableGen's error "Ran out of lanemask bits" in order to use more than 32 subregisters per register
...n 32 lanes (32 subregisters per vector
> register) in TableGen, llc and opt. For example, I use SIMD instructions with types
> v128i16 and v512i16.
>
> An important questions I have is if it is OK to add the types IIT_V128 = 37, IIT_V256
> = 38 like I did below:
> enum IIT_Info {
> ...
> IIT_V2 = 9,
> IIT_V4 = 10,
> IIT_V8 = 11,
> IIT_V16 = 12,
> IIT_V32 = 13,
> ...
> IIT_V64 = 16,
> IIT_V1 = 28,
> IIT_VEC_OF_PTRS_TO_ELT = 33,
>...
2016 Sep 18
4
Addressing TableGen's error "Ran out of lanemask bits" in order to use more than 32 subregisters per register
...bleGen/IntrinsicEmitter.cpp,
comes from the fact there is no IIT_V128 (nor IIT_V256), and they is a
switch case using them in method static void EncodeFixedType(Record *R,
std::vector<unsigned char> &ArgCodes, std::vector<unsigned char> &Sig).
Is there any reason these enum IIT_Info ( IIT_V128, IIT_V256) are not
added in file /IntrinsicEmitter.cpp?
Thank you,
Alex
On Tue, Sep 13, 2016 at 1:47 AM, Matthias Braun <mbraun at apple.com> wrote:
>
> > On Sep 8, 2016, at 6:37 AM, Alex Susu via llvm-dev <
> llvm-dev at lists.llvm.org> wrote:
> >...
2016 Sep 08
2
Addressing TableGen's error "Ran out of lanemask bits" in order to use more than 32 subregisters per register
Hello.
In my TableGen back end description I need to use more than 32 (e.g., 128, 1024, etc)
subregisters per register for my research SIMD processor. I have used so far with success
32 subregisters.
However, when using 128 subregisters when I now give the command:
llvm-tblgen -gen-register-info Connex.td
I get an error message "error:Ran out of lanemask bits to