Displaying 11 results from an estimated 11 matches for "iiopnum".
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...ug 24, 2015, at 4:46 PM, Ryan Taylor <ryta1203 at gmail.com> wrote:
>
> Here is the snippet that matters:
>
> void
> InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
> SDValue Op,
> unsigned IIOpNum,
> const MCInstrDesc *II,
> DenseMap<SDValue, unsigned> &VRBaseMap,
> bool IsDebug, bool IsClone, bool IsCloned) {
> //llvm::errs() << "Op = ";
> //Op.dump...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...yan Taylor <ryta1203 at gmail.com> wrote:
>>
>> Here is the snippet that matters:
>>
>> void
>> InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
>> SDValue Op,
>> unsigned IIOpNum,
>> const MCInstrDesc *II,
>> DenseMap<SDValue, unsigned> &VRBaseMap,
>> bool IsDebug, bool IsClone, bool
>> IsCloned) {
>> //llvm::errs() << "Op =...
2015 Aug 25
4
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...t;mailto:ryta1203 at gmail.com>> wrote:
>>
>> Here is the snippet that matters:
>>
>> void
>> InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
>> SDValue Op,
>> unsigned IIOpNum,
>> const MCInstrDesc *II,
>> DenseMap<SDValue, unsigned> &VRBaseMap,
>> bool IsDebug, bool IsClone, bool IsCloned) {
>> //llvm::errs() << "Op = ";...
2015 Aug 24
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
> On Aug 24, 2015, at 1:30 PM, Ryan Taylor <ryta1203 at gmail.com> wrote:
>
> I'm trying to do something like this:
>
> // Dst = NewVReg's reg class
> // *II = MCInstrDesc
> // IIOpNum = II Operand Num
>
> if (TRI->getCommonSubClass(DstRC, TRI->getRegClass(II->OpInfo[IIOpNum].RegClass)) == DstRC)
> MRI->setRegClass(VReg, DstRC);
> else
> BuildMI(... TargetOpcode::COPY...)
>
> The condition is trying to reset the reg class if the DstRC...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...>>>>>>>
>>>>>>> void
>>>>>>> InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
>>>>>>> SDValue Op,
>>>>>>> unsigned IIOpNum,
>>>>>>> const MCInstrDesc *II,
>>>>>>> DenseMap<SDValue, unsigned>
>>>>>>> &VRBaseMap,
>>>>>>> bool IsDeb...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...>>>
>>>>>>>> void
>>>>>>>> InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
>>>>>>>> SDValue Op,
>>>>>>>> unsigned IIOpNum,
>>>>>>>> const MCInstrDesc *II,
>>>>>>>> DenseMap<SDValue, unsigned>
>>>>>>>> &VRBaseMap,
>>>>>>>>...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...;>>>>>>>> void
>>>>>>>>> InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
>>>>>>>>> SDValue Op,
>>>>>>>>> unsigned IIOpNum,
>>>>>>>>> const MCInstrDesc *II,
>>>>>>>>> DenseMap<SDValue, unsigned>
>>>>>>>>> &VRBaseMap,
>>>>>>>>>...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...;>>>>> void
>>>>>>>>>> InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
>>>>>>>>>> SDValue Op,
>>>>>>>>>> unsigned IIOpNum,
>>>>>>>>>> const MCInstrDesc *II,
>>>>>>>>>> DenseMap<SDValue, unsigned>
>>>>>>>>>> &VRBaseMap,
>>>>>>>>>...
2015 Aug 25
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
...;>> void
>>>>>>>>>>> InstrEmitter::AddRegisterOperand(MachineInstrBuilder &MIB,
>>>>>>>>>>> SDValue Op,
>>>>>>>>>>> unsigned IIOpNum,
>>>>>>>>>>> const MCInstrDesc *II,
>>>>>>>>>>> DenseMap<SDValue, unsigned>
>>>>>>>>>>> &VRBaseMap,
>>>>>>...
2015 Aug 24
2
[LLVMdev] TableGen Register Class not matching for MI in 3.6
> On Aug 22, 2015, at 9:10 AM, Ryan Taylor <ryta1203 at gmail.com> wrote:
>
> One last question regarding this please.
>
> Why aren't we simply changing the register class in AddRegisterOperand instead of building a new COPY? I admit I haven't thought this out but for my test cases so far this works just fine and reduces the number of ASM mov instructions that are
2009 Mar 15
5
[LLVMdev] Overlapping register classes
Hi,
I am writing a backend for the Blackfin processor from Analog Devices. I
just started so I still have a lot to learn about the code generator. So
far, I can compile test/CodeGen/Generic/BasicInstrs.ll correctly, but
that is about it.
The Blackfin 32-bit registers divide naturally into several classes. I
have modelled these register classes without knowing anything about what
the code