search for: iiimul

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2011 Aug 15
2
[LLVMdev] Question on instruction itineraries
...cy of 2 cycles for multiplications fully pipelined (so it can start a new one after one cycle) First of all, is there a document that describes the instruction itinerary model in some detail ? For example looking at MBlaze target MBlaeSchedule.td I can see something like MblazeSchedule.td ... def IIImul : InstrItinClass; ... InstrItinData<IIImul , [InstrStage<17, [IMULDIV]>]>, Does that mean Mul's are expected to have a latency of 17 clks ? Mips target has something similar. In Mblaze case I can see the result being used the very next cycle mul...
2011 Aug 16
0
[LLVMdev] Question on instruction itineraries
...; fully pipelined (so it can start a new one after one cycle) > First of all, is there a document that describes the instruction itinerary > model in some detail ? > For example looking at MBlaze target MBlaeSchedule.td I can see something > like > MblazeSchedule.td > ... > def IIImul             : InstrItinClass; > ... >   InstrItinData<IIImul             , [InstrStage<17, [IMULDIV]>]>, > > Does that mean Mul's are expected to have a latency of 17 clks ? Mips target > has something similar. Yes. > In Mblaze case I can see the result being use...
2011 Aug 17
1
[LLVMdev] Question on instruction itineraries
...one after one cycle) > > First of all, is there a document that describes the instruction > itinerary > > model in some detail ? > > For example looking at MBlaze target MBlaeSchedule.td I can see something > > like > > MblazeSchedule.td > > ... > > def IIImul : InstrItinClass; > > ... > > InstrItinData<IIImul , [InstrStage<17, [IMULDIV]>]>, > > > > Does that mean Mul's are expected to have a latency of 17 clks ? Mips > target > > has something similar. > > Yes. > > &g...