Displaying 5 results from an estimated 5 matches for "iic_sse_prefetch".
2018 Mar 19
4
Generating a custom opcode from an LLVM intrinsic
...d simply produce
a warning). Then my guess is that I should use something like:
def CACHEADD : I<0x16, FORMAT, (outs), (ins),
ASM, [(int_cache_add)]>, PD;
where FORMAT comes from
http://legup.eecg.utoronto.ca/doxygen/namespacellvm_1_1X86II.html
and ASM = ???
and i deleted IIC_SSE_PREFETCH (because I'm not sure what this flag
indicates, but I assume it's not needed).
I'm not sure what that PD is or if it should stay.
Looking for input on this! Clearly it's not correct as-is, but I feel like
I'm at least understanding parts of it. Thanks!
For posterity, this page...
2018 Mar 19
0
Generating a custom opcode from an LLVM intrinsic
...printed in a textual listing of the
assembly. The curly braces you see in some text strings like
"adcx{l}\t{$src, $dst|$dst, $src}" are there to provide different operand
orders for at&t syntax vs intel syntax. Anything after $ matches the name
in the outs/in part of the instruction.
IIC_SSE_PREFETCH is part of the scheduler system to provide
latency/throughput information about the instruction.
PD indicates the instruction should be on the 0x0f two byte opcode map with
a 0x66 prefix.
Most common other values in place of PD
TB - 0x0f opcode map no prefix(0x66, 0xf2, 0xf3) and use of one of th...
2018 Mar 20
1
Generating a custom opcode from an LLVM intrinsic
...of the
> assembly. The curly braces you see in some text strings like
> "adcx{l}\t{$src, $dst|$dst, $src}" are there to provide different operand
> orders for at&t syntax vs intel syntax. Anything after $ matches the name
> in the outs/in part of the instruction.
>
> IIC_SSE_PREFETCH is part of the scheduler system to provide
> latency/throughput information about the instruction.
>
> PD indicates the instruction should be on the 0x0f two byte opcode map
> with a 0x66 prefix.
>
> Most common other values in place of PD
> TB - 0x0f opcode map no prefix(0x66,...
2018 Mar 18
0
Generating a custom opcode from an LLVM intrinsic
...rInfo.td. If you look for int_x86_* in any X86Instr*.td you can
find others.
let Predicates = [HasCLFLUSHOPT], SchedRW = [WriteLoad] in
def CLFLUSHOPT : I<0xAE, MRM7m, (outs), (ins i8mem:$src),
"clflushopt\t$src", [(int_x86_clflushopt addr:$src)],
IIC_SSE_PREFETCH>, PD;
let Predicates = [HasCLWB], SchedRW = [WriteLoad] in
def CLWB : I<0xAE, MRM6m, (outs), (ins i8mem:$src), "clwb\t$src",
[(int_x86_clwb addr:$src)], IIC_SSE_PREFETCH>, PD;
The encoding information for the binary output is buried in these
definitions...
2018 Mar 18
2
Generating a custom opcode from an LLVM intrinsic
Hello all. LLVM newbie here. If anything seems glaringly wrong with my use
of LLVM, that's probably why.
Here's what I'm trying to do. I have modified the gem5 simulator to accept
a "new" x86 instruction. I've done this by just reserving the opcode in
gem5's ISA specification, just as all other instructions are specified.
I'm trying to get an LLVM backend to