search for: iic_mov_mem

...ents. so in x86instrinfo.td i wrote; def VMOV_256B_RM : I<0x6F, MRMSrcMem, (outs VR2048:$dst), (ins i32mem:$src), "vmov_256B_rm\t{$src, $dst|$dst, $src}", [(set VR2048:$dst, (v64i32 (scalar_to_vector (loadi32 addr:$src))))], IIC_MOV_MEM>, EVEX; def VMOV_256B_MR : I<0x7F, MRMDestMem, (outs), (ins i32mem:$dst, VR2048:$src), "vmov_256B_mr\t{$src, $dst|$dst, $src}", [(store (i32 (bitconvert VR2048:$src)), addr:$dst)], IIC_MOV_MEM>, EVEX; here i have already define VR2048 in...

...et/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -1412,7 +1412,7 @@ let SchedRW = [WriteStore] in { def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), "mov{b}\t{$src, $dst|$dst, $src}", [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>; -def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), +def MOV16mr : I<0x89, MRMDestMem, (outs i16mem:$dst), (ins GR16:$src), "mov{w}\t{$src, $dst|$dst, $src}", [(store GR16:$src, addr:$dst)], IIC_MOV_MEM>, OpSize16; def...

...1, VK64WM:$mask, i2048mem:$src2), "GATHER_256B\t{$src2, {$dst} {${mask}}|${dst} {${mask}}, $src2}", [(set VR_2048:$dst, VK64WM:$mask_wb, (v64i32 (masked_gather (VR_2048:$src1), VK64WM:$mask, addr:$src2)))], IIC_MOV_MEM>, TA; def: Pat<(v64f32 (masked_gather (VR_2048:$src1), (VK64WM:$mask),(addr:$src2))), (GATHER_256B VR_2048:$src1, VK64WM:$mask, addr:$src2)>; Now getting this error: llvm-tblgen: /utils/TableGen/X86RecognizableInstr.cpp:687: void llvm::X86Disassembler::RecognizableInstr::emitInstructio...

...KRCWM:$mask, ins i2048mem:$src2), "GATHER_256B\t{$src2, {$dst}{${mask}}|${dst} {${mask}}, $src2}"), [(set VR_2048:$dst, _.KRCWM:$mask_wb, (v64i32 (GatherNode (VR_2048:$src1), _.KRCWM:$mask, VR_2048:$src2))], IIC_MOV_MEM>, TA; def: Pat<(v64f32 (GatherNode addr:$src2)), (GATHER_256B addr:$src2)>; Thank You On Mon, Aug 7, 2017 at 2:57 AM, Craig Topper <craig.topper at gmail.com> wrote: > masked_gather returns two results. The data and the modified mask. Note > the $dst and the $mask_wb in the...

...ement gather for v64i32. i wrote following code. def GATHER_256B : I<0x68, MRMSrcMem, (outs VR_2048:$dst), (ins i2048mem:$src), "GATHER_256B\t{$src, $dst|$dst, $src}", [(set VR_2048:$dst, (v64i32 (masked_gather addr:$src)))], IIC_MOV_MEM>, TA; def: Pat<(v64f32 (masked_gather addr:$src)), (GATHER_256B addr:$src)>; Also i wrote this line in isellowering.h setOperationAction(ISD::MGATHER, MVT::v64i32, Legal); But I am getting following error: llvm-tblgen: /utils/TableGen/CodeGenDAGPatterns.cpp:21...

...1024, (add R_0_V_0, R_1_V_0, R_2_V_0)>; def STORE_DWORD : I<0x70, MRMDestMem, (outs), (ins i2048mem:$dst, VRR128:$src), "STORE_DWORD\t{$src, $dst|$dst, $src}", [(store (v32i32 (bitconvert VRR128:$src)), addr:$dst)], IIC_MOV_MEM>, TA; def: Pat<(store (v32f32 (bitconvert (VRR128:$src))), addr:$dst), (STORE_DWORD addr:$dst, VRR128:$src)>; but getting the following error; STORE_DWORD: (st (bitconvert:v32i32 VRR128:{v32i32:v32f32}:$src), addr:iPTR:$dst)<<P:Predicate_unindexedstore>><<P:Predicate_...

...0, R_2_V_0)>; >> >> def STORE_DWORD : I<0x70, MRMDestMem, (outs), (ins i2048mem:$dst, >> VRR128:$src), >> "STORE_DWORD\t{$src, $dst|$dst, $src}", >> [(store (v32i32 (bitconvert VRR128:$src)), >> addr:$dst)], IIC_MOV_MEM>, TA; >> >> >> >> def: Pat<(store (v32f32 (bitconvert (VRR128:$src))), addr:$dst), >> (STORE_DWORD addr:$dst, VRR128:$src)>; >> >> but getting the following error; >> STORE_DWORD: (st (bitconvert:v32i32 VRR128:{v32i32:v32f32}:$src), >>...

Hi Jun, I'm not sure how to fix this yet, but this looks incorrectly defined in lib/Target/X86/X86InstrInfo.td: def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src), "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, Requires<[In32BitMode]>; This instruction can be REX-prefixed for a 64-bit move, and that also doesn't appear to be defined anywhere. I would file a bugzilla in the x86 component and cc Craig Topper, the x86 disasm/codegen expert. On Wed, Nov 27, 2013 at 8:5...

Hi, With objdump, i have this (Intel syntax) 64 a1 00 00 00 00 mov eax,fs:0x0 However, if I pass above string to llvm-mc, I would have: $ echo "0x64 0xa1 0x00 0x00 0x00 0x00"|./Release+Asserts/bin/llvm-mc -disassemble -arch=x86 --output-asm-variant=1 .text mov eax, dword ptr [0] You can see a big difference. This is on the latest code. Any idea how to

...gt;wrote: > Hi Jun, > > I'm not sure how to fix this yet, but this looks incorrectly defined in > lib/Target/X86/X86InstrInfo.td: > > def MOV32o32a : Ii32 <0xA1, RawFrm, (outs), (ins offset32:$src), > "mov{l}\t{$src, %eax|eax, $src}", [], IIC_MOV_MEM>, > Requires<[In32BitMode]>; > > This instruction can be REX-prefixed for a 64-bit move, and that also > doesn't appear to be defined anywhere. > > I would file a bugzilla in the x86 component and cc Craig Topper, the x86 > disasm/codegen exper...

...t; def STORE_DWORD : I<0x70, MRMDestMem, (outs), (ins i2048mem:$dst, >>>> VRR128:$src), >>>> "STORE_DWORD\t{$src, $dst|$dst, $src}", >>>> [(store (v32i32 (bitconvert VRR128:$src)), >>>> addr:$dst)], IIC_MOV_MEM>, TA; >>>> >>>> >>>> >>>> def: Pat<(store (v32f32 (bitconvert (VRR128:$src))), addr:$dst), >>>> (STORE_DWORD addr:$dst, VRR128:$src)>; >>>> >>>> but getting the following error; >>>> STORE_DWORD...

...lexPattern<iPTR, 5, "selectAddr", [], [SDNPWantParent]>; The derefencing mov instruction looks like this: def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), "mov{l}\t{$src, $dst|$dst, $src}", [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32; So it expects a source address of type 'addr' which is 8 bytes. This leads to the following code being emitted when I apply my solution to problem 1: mov (%rcx),%eax In other words, the upper bits are not ignored. I am currently not sure what is the best place to...

...uot;selectAddr", [], > [SDNPWantParent]>; > The derefencing mov instruction looks like this: > def MOV32rm : I<0x8B, MRMSrcMem, (outs GR32:$dst), (ins i32mem:$src), > "mov{l}\t{$src, $dst|$dst, $src}", > [(set GR32:$dst, (loadi32 addr:$src))], IIC_MOV_MEM>, OpSize32; > So it expects a source address of type 'addr' which is 8 bytes. This > leads to the following code being emitted when I apply my solution to > problem 1: > mov (%rcx),%eax > In other words, the upper bits are not ignored. > > > I am current...

...X86/X86InstrInfo.td > > @@ -1412,7 +1412,7 @@ let SchedRW = [WriteStore] in { > > def MOV8mr : I<0x88, MRMDestMem, (outs), (ins i8mem :$dst, GR8 :$src), > > "mov{b}\t{$src, $dst|$dst, $src}", > > [(store GR8:$src, addr:$dst)], IIC_MOV_MEM>; > > -def MOV16mr : I<0x89, MRMDestMem, (outs), (ins i16mem:$dst, GR16:$src), > > +def MOV16mr : I<0x89, MRMDestMem, (outs i16mem:$dst), (ins GR16:$src), > > "mov{w}\t{$src, $dst|$dst, $src}", > > [(store GR16:$src, addr:...

...e my vector instructions so i wrote; def VMOV_256B_RM : I<0x6F, MRMSrcMem, (outs VR2048:$dst), (ins i32mem:$src), "vmov_256B_rm\t{$src, $dst|$dst, $src}", [(set VR2048:$dst, (v64i32 (scalar_to_vector (loadi32 addr:$src))))], IIC_MOV_MEM>, EVEX; def VMOV_256B_MR : I<0x7F, MRMDestMem, (outs), (ins i32mem:$dst, VR2048:$src), "vmov_256B_mr\t{$src, $dst|$dst, $src}", [(store (i32 (bitconvert VR2048:$src)), addr:$dst)], IIC_MOV_MEM>, EVEX; in x86instrinfo.td; when i build i g...

...$dst, $src}", >>>>>>>>>>>>>> [(set VR2048:$dst, (v64i32 >>>>>>>>>>>>>> (scalar_to_vector (loadi32 addr:$src))))], >>>>>>>>>>>>>> IIC_MOV_MEM>, EVEX; >>>>>>>>>>>>>> >>>>>>>>>>>>>> def VMOV_256B_MR : I<0x7F, MRMDestMem, (outs), (ins >>>>>>>>>>>>>> i32mem:$dst, VR2048:$src), >>>>>>>>&gt...

...type of its memory operands? As an example, consider the following description of MOV32mr (from X86InstrInfo.td) def MOV32mr : I<0x89, MRMDestMem, (outs), (ins i32mem:$dst, GR32:$src), "mov{l}\t{$src, $dst|$dst, $src}", [(store GR32:$src, addr:$dst)], IIC_MOV_MEM>, OpSize32; or that of MOVSX64rm (from X86InstrExtension.td) def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src), "movs{lq|xd}\t{$src, $dst|$dst, $src}", [(set GR64:$dst, (sextloadi64i32 addr:$src))], IIC_MOVSX>,...

...VR2048:$dst), (ins >>>> i32mem:$src), >>>> "vmov_256B_rm\t{$src, $dst|$dst, $src}", >>>> [(set VR2048:$dst, (v64i32 (scalar_to_vector >>>> (loadi32 addr:$src))))], >>>> IIC_MOV_MEM>, EVEX; >>>> >>>> def VMOV_256B_MR : I<0x7F, MRMDestMem, (outs), (ins i32mem:$dst, >>>> VR2048:$src), >>>> "vmov_256B_mr\t{$src, $dst|$dst, $src}", >>>> [(store (i32 (bitconvert VR204...