Displaying 4 results from an estimated 4 matches for "iic_iload_i".
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iic_iload_r
2011 Oct 07
1
[LLVMdev] Multiple-Pipeline Itinerary
In the example provided:
// InstrItinData<IIC_iLoad_i , [InstrStage<1, [A9_Pipe1]>,
// InstrStage<1, [A9_AGU]>],
// [3, 1], [A9_LdBypass]>,
If there is an operand dependency, does the scheduler assume that the
instruction is held in A9_Pipe1 or in A9_AGU until the operand is re...
2012 Mar 26
1
[LLVMdev] Disassembly broken for thumb LDR
..., [pc, #380]
(provided by Apple's otool).
I've traced the issue down to ARMInstrThumb.td:
// A8.6.57 & A8.6.60
defm tLDR : thumb_ld_rr_ri_enc<0b100, 0b0110, t_addrmode_rrs4,
t_addrmode_is4, AddrModeT1_4,
IIC_iLoad_r, IIC_iLoad_i, "ldr",
UnOpFrag<(load node:$Src)>>;
In the generated TableGen output the issue lies around line 4992:
4992 case ARM::tUXTH: printOperand(MI, 1, O); break;
As the operand is not enough in this case.
I'm pretty stuck at the TableGen deci...
2011 Oct 06
2
[LLVMdev] Multiple-Pipeline Itinerary
Anton,
Thanks!
What is the difference between Reserved and Required?
-Hal
On Fri, 2011-10-07 at 00:11 +0400, Anton Korobeynikov wrote:
> Hello Hal.
>
> > Is there a way to express a multiple pipeline itinerary using the
> > current scheme
> Yes, surely
>
> > (maybe some trick with setting NextCycles = 0)?
> Yep!
>
> > Specifically, consider a case
2011 Oct 06
0
[LLVMdev] Multiple-Pipeline Itinerary
Hal,
> What is the difference between Reserved and Required?
Think about them like read/write locks.
E.g. if FU is Reserved (=read lock) is can be Reserved multiple times,
but never Required.
If FU is Required (=write lock) it cannot be neither Reserved nor Required.
--
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University