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iic_int
2018 Apr 05
1
A9 Scheduler
..."BICrr")>;
This same instruction is defined in the ARMInstrInfo.td as inheriting from
AsI1_bin_irs (shown below) which, in turn, associates Sched<[WriteALU,
ReadALU]> with the instruction.
defm AND : AsI1_bin_irs<0b0000, "and",
IIC_iBITi, IIC_iBITr, IIC_iBITsr, and, 1>;
In my mind, we have latencies defined from the ProcessorItineraries,
latencies defined in the SchedReadWrite representation which are mapped
through SchedAlias to the ANDri and, in the end, a mapping (or overriding?)
of the latencies in the Itineraries by the...