search for: iialu

Here is a simple place I wanted to use it. ... On multiply, the result implicit is placed in a 64 bit hi/lo register. // // Format: MFLO rx MIPS16e // Purpose: Move From LO Register // To copy the special purpose LO register to a GPR. // def Mflo16: FRR16_M_ins<0b10010, "mflo", IIAlu> { let Uses = [LO]; let neverHasSideEffects = 1; } // // Pseudo Instruction for mult // def MultRxRy16: FMULT16_ins<"mult", IIAlu> { let isCommutable = 1; let neverHasSideEffects = 1; let Defs = [HI, LO]; } def: Mips16Pattern<(mul CPU16Regs:$l, CPU16Regs:$r),...

...attern. > > def op_la : Operand<i32>; > > def LA : > FI<0x09, (outs CPURegs:$dst), (ins op_la:$addr0, op_la:$addr1), > "la $dst, $addr0", [(set CPURegs:$dst, > (add (MipsHi tglobaladdr:$addr0), (MipsLo > tglobaladdr:$addr1)))], IIAlu>; > > Note that you still need to find a way to print "g1" instead of "%hi(g1)". > > On Wed, Oct 5, 2011 at 4:01 PM, Gang-Ryung Uh <guh at boisestate.edu> wrote: > > Hi, > > In order to emit "la $4,ADDR" instead of lui followed by...

...hat is the case, you can add this pattern. def op_la : Operand<i32>; def LA : FI<0x09, (outs CPURegs:$dst), (ins op_la:$addr0, op_la:$addr1), "la $dst, $addr0", [(set CPURegs:$dst, (add (MipsHi tglobaladdr:$addr0), (MipsLo tglobaladdr:$addr1)))], IIAlu>; Note that you still need to find a way to print "g1" instead of "%hi(g1)". On Wed, Oct 5, 2011 at 4:01 PM, Gang-Ryung Uh <guh at boisestate.edu> wrote: > Hi, >      In order to emit "la $4,ADDR" instead of lui followed by addiu to load > the data...

...6 : Operand<i16> { let DecoderMethod= "DecodeSimm16"; let OperandType = "OPERAND_IMMEDIATE"; } class SII<bits&lt;6> op, string instr_asm, Operand Imm> : FI<op, (outs), (ins Imm:$val), !strconcat(instr_asm, &quot;\t$val&quot;), [], IIAlu> { let rs = 0; let rt = 0; } def MOV : SII<0x21, "mov", simm16>; def : TARGETPat<(int_my_builtin_function_name (imm:$val)), (MOV imm:$val)>; I just found that the base Instruction class has Defs and Uses lists where it is possible to pass the Registers, but actu...

What have you tried? On Sun, Sep 16, 2012 at 3:34 PM, Kotler, Reed <rkotler at mips.com> wrote: > This Pattern class says it's possible but seems just to not work or maybe I'm using it incorrectly. > > Probably I will go and fix it when I'm done with mips16. > > > ________________________________________ > From: Hal Finkel [hfinkel at anl.gov] > Sent:

This Pattern class says it's possible but seems just to not work or maybe I'm using it incorrectly. Probably I will go and fix it when I'm done with mips16. ________________________________________ From: Hal Finkel [hfinkel at anl.gov] Sent: Sunday, September 16, 2012 10:59 AM To: Anton Korobeynikov Cc: Kotler, Reed; LLVM-Dev ‎[llvmdev at cs.uiuc.edu]‎ Subject: Re: [LLVMdev] Pattern

...tern. > > def op_la : Operand<i32>; > > def LA : > FI<0x09, (outs CPURegs:$dst), (ins op_la:$addr0, op_la:$addr1), > "la $dst, $addr0", [(set CPURegs:$dst, > (add (MipsHi tglobaladdr:$addr0), (MipsLo > tglobaladdr:$addr1)))], IIAlu>; > > Note that you still need to find a way to print "g1" instead of "%hi(g1)". > > On Wed, Oct 5, 2011 at 4:01 PM, Gang-Ryung Uh <guh at boisestate.edu> wrote: > > Hi, > > In order to emit "la $4,ADDR" instead of lui followed b...

Hi, In order to emit "la $4,ADDR" instead of lui followed by addiu to load the data address, could you advise what is proper way to revise td files in the MIPS target? Thanks, -- Gang-Ryung Uh, Associate Professor Department of Computer Science College of Engineering, Boise State Univerisity tel: 1 208 426-5691 e-mail:guh at boisestate.edu http://cs.boisestate.edu/~uh

...Operand<i32>; > > > > def LA : > > FI<0x09, (outs CPURegs:$dst), (ins op_la:$addr0, op_la:$addr1), > > "la $dst, $addr0", [(set CPURegs:$dst, > > (add (MipsHi tglobaladdr:$addr0), (MipsLo > > tglobaladdr:$addr1)))], IIAlu>; > > > > Note that you still need to find a way to print "g1" instead of > "%hi(g1)". > > > > On Wed, Oct 5, 2011 at 4:01 PM, Gang-Ryung Uh <guh at boisestate.edu> > wrote: > > > Hi, > > > In order to emit "la $...

...tABDIn<string asmstr, DAGOperand srcA, DAGOperand srcB, >> DAGOperand >> dstD, list<dag> pattern> >> : A_B_D<(outs), (ins srcA:$srcA, srcB:$srcB, dstD:$dstD), >> !strconcat(asmstr, "\t$srcA, $srcB, $dstD"), pattern, >> IIAlu> >> { >> let mayStore = 1; >> let mayLoad = 1; >> } >> >> >> On Wed, Feb 15, 2017 at 2:24 PM, Manuel Jacob <me at manueljacob.de> >> wrote: >> >>> On 2017-02-15 19:54, Ryan Taylor wrote: >>> >>>&g...

...instruction and now I'm getting "UNREACHABLE executed!" when trying to compile the code. The only change I made was to add the following two lines next to the square root lines in the code (FPU and sqrt are enabled in llc): def FSQRT : ArithF2<0x16, 0x300, "fsqrt ", IIAlu>; def FNEG : ArithF2<0x16, 0x300, "fneg ", IIAlu>; // added for fneg and def : Pat<(fsqrt FGR32:$V), (FSQRT FGR32:$V)>; def : Pat<(fneg FGR32:$V), (FNEG FGR32:$V)>; // added for fneg Does anyone know what common causes of "UNREACHABLE executed!"...

...))), addr16:$dstD)]>; ..... } class SetABDIn<string asmstr, DAGOperand srcA, DAGOperand srcB, DAGOperand dstD, list<dag> pattern> : A_B_D<(outs), (ins srcA:$srcA, srcB:$srcB, dstD:$dstD), !strconcat(asmstr, "\t$srcA, $srcB, $dstD"), pattern, IIAlu> { let mayStore = 1; let mayLoad = 1; } On Wed, Feb 15, 2017 at 2:24 PM, Manuel Jacob <me at manueljacob.de> wrote: > On 2017-02-15 19:54, Ryan Taylor wrote: > >> Thanks for your reply. >> >> We are propagating sign info to tablegen currently using >&g...

Thanks for your reply. We are propagating sign info to tablegen currently using BinaryWithFlagsSDNode.Flags.hasNoSignedWrap atm. I imagine (I have not looked) they are printed according to instruction in AsmPrinter.cpp (pure speculation). I'm still confused as to why 0x7FFF is ok to match 16 bit int but not 0x8000? Thanks. On Wed, Feb 15, 2017 at 1:44 PM, Manuel Jacob <me at