search for: ii_load1

...from certain memory locations take a long time to complete (on the order of 150 clock cycles). Since we don't have a way to tell at compile time if the address being loaded from lies in slow or fast memory, I've gone ahead and made all of the load numbers high, such as: InstrItinData< II_LOAD1, [InstrStage<150, [AGU]>]>, However, I see that there is another field which I haven't specified where operand latencies are specified. Here's an example from ARMScheduleA8.td: InstrItinData<IIC_iALUi ,[InstrStage<1, [A8_Pipe0, A8_Pipe1]>], [2, 2]>, Now I'...

...ddr:$addr)), > (load (movimm tglobaladdr:$addr), GRP)>; > I'm not entirely sure what to replace 'load' with in the patterns above. I notice that we have these defm's in our XSTGInstrInfo.td file: defm LOADI64 : LoadOp< 0b1001010, "load", OpInfo_I64, II_LOAD1 >; defm LOADF64 : LoadOp< 0b1001010, "load", OpInfo_F64, II_LOAD1 >; defm LOADI32 : LoadOp< 0b1001010, "load", OpInfo_I32, II_LOAD1 >; defm LOADF32 : LoadOp< 0b1001010, "load", OpInfo_F32, II_LOAD1 >; defm LOADI16 : LoadOp< 0b1001010, "load...

...me >> to complete (on the order of 150 clock cycles). Since we don't have a way >> to tell at compile time if the address being loaded from lies in slow or >> fast memory, I've gone ahead and made all of the load numbers high, such as: >> >> InstrItinData< II_LOAD1, [InstrStage<150, [AGU]>]>, >> >> However, I see that there is another field which I haven't specified >> where operand latencies are specified. Here's an example from >> ARMScheduleA8.td: >> >> InstrItinData<IIC_iALUi ,[InstrStage<1...

On Wed, Jan 13, 2016 at 2:08 PM, Krzysztof Parzyszek via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 1/13/2016 2:26 PM, Phil Tomson via llvm-dev wrote: > >> I've got this PseudoOp defined: >> >> def SDT_RELADDR : SDTypeProfile<1, 2, [SDTCisInt<0>, SDTCisInt<1>]>; >> def XSTGRELADDR :