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2010 Jul 06
0
[LLVMdev] Question on the use of TableGen
Hi all,
I'm trying to create a new backend for a processor, and I start with
modifying the existing backends like MIPS and Microblaze.
I have a problem when I try to add a register class in the Target's register
description, it looks like this:
def IGPRegs : RegisterClass<"MBlaze", [v8i16], 128, [PR0, PR1, PR2, PR3]>;
// PR0 - PR3 are registers defined before
I want to have a new integer register file for a different type, e.g. v8i16.
But then I got errors when running tblgen.
Here is the error I got when modifying the MBlaze bac...