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Hi, The 'br' instruction has the syntax: br i1 <cond>, label <iftrue>, label <iffalse> br label <dest> ; Unconditional branch If we know <cond>'s type must be 'i1', <iftrue><iffalse><dest> have to be of type 'label', why does the syntax have to specify them? lib/...

...t a conditional branch in the middle of a basic block. To that end, I am doing these steps: (1) Split the basic block: bb->splitBasicBlock() (2) Remove the old terminator: succ->removePredecessor(bb) bb->getTerminator()->getParent() (3) Adding a new terminator: BranchInst::Create(ifTrue, ifFalse, cnd, "", bb); That seems to work, but later passes are dieing. When I dump the function from my debugger, I notice that the new block (the second half of the block I split) has a "<null operand>" as a predecessor. What am I doing wrong? Here's what bb-&g...

...; bb->getTerminator()->getParent() Assuming that the new block will still be a successor of the old block (just not the unique successor), all you really need to do is: BasicBlock* succ = bb->splitBasicBlock(); bb->getTerminator()->eraseFromParent(); BranchInst::Create(<ifTrue>, <ifFalse>, <cond>, bb); John.

Hello, All, Mac OS 10.6.5 R64 2.11.1 This works as expected: f1 = c(0.084, 0.099, 0) data= data.frame(f1) data$f1=with(data,ifelse(f1==0, 0.0001, f1)) data f1 1 0.0840 2 0.0990 3 0.0001 Substituting ''f1==0'' with ''T'' produces the expected result: f1 = c(0.084, 0.099, 0) data= data.frame(f1) data$f1=with(data,ifelse(T, 0.0001, f1)) data f1 1 1e-04

...el IRs (not machine dependent, not in the code-gen stage), is it reasonable to assume that ALL LLVM IRs that have a result field will have potential to write stack? E.g. <result> = add<ty> <op1>,<op2> /; yields {ty}:result/ br i1<cond>, label<iftrue>, label<iffalse> br label<dest> /; Unconditional branch/ ADD can (potential) write stack to store its result, while BR will NEVER write stack because its doesn't have a result. Thank you Chuck On 1/21/2011 5:33 PM, John Criswell wrote: > On 1/21/11 2:50...

Thank you for the suggestion, Bill. The result is not quite what I would like. Here's sample code for you or anyone else who may be interested: Al1 = c('A','C','C','C') Al2 = c('G','G','G','T') Freq1 = c(0.0078,0.0567,0.9434,0.9908) MAF = c(0.0078,0.0567,0.0566,0.0092) m1 = data.frame(Al1=Al1,

On 1/21/11 2:50 PM, Chuck Zhao wrote: > I need to figure out all LLVM Instructions that may write to memory. > > In http://llvm.org/docs/tutorial/OCamlLangImpl7.html, it mentions that > "In LLVM, all memory accesses are explicit with load/store > instructions, and it is carefully designed not to have (or need) an > "address-of" operator." > > I take

I need to figure out all LLVM Instructions that may write to memory. In http://llvm.org/docs/tutorial/OCamlLangImpl7.html, it mentions that "In LLVM, all memory accesses are explicit with load/store instructions, and it is carefully designed not to have (or need) an "address-of" operator." I take this as "StoreInst is the only one that writes to memory". However,