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...dated in) 2009. >>>>>> + >>>>>> > +//===---------------------------------------------------------------------- > ===// >>>>>> +// Functional units on the PowerPC 440/450 chip sets >>>>>> +// >>>>>> +def IFTH1 : FuncUnit; // Fetch unit 1 >>>>>> +def IFTH2 : FuncUnit; // Fetch unit 2 >>>>>> +def PDCD1 : FuncUnit; // Decode unit 1 >>>>>> +def PDCD2 : FuncUnit; // Decode unit 2 >>>>>> +def DISS1 : FuncUnit; // Issue unit 1 >>...

...D=25] in other words, it produces a set of load, add, store triples, non-interleaved, in order. The problem is that the result of the load is not immediately available, and either is the result of the add. The loads are covered by the itinerary: InstrItinData<LdStLFD , [InstrStage<1, [IFTH1, IFTH2]>, InstrStage<1, [PDCD1, PDCD2]>, InstrStage<1, [DISS1, DISS2]>, InstrStage<1, [LRACC]>, InstrStage<1, [AGEN]>,...