search for: ifconverter

Hi all, If you have an out of tree target and use the IfConverter be aware of a new API call "getPredictationCost“ that you might want to implement: After commit r191671: IfConverter: Use TargetSchedule for instruction latencies For targets that have instruction itineraries this means no change. Targets that move over to the new schedule m...

greened at obbligato.org (David A. Greene) writes: > Updating LLVM - no local changes > -------------------------------- > > To update your clone to the latest LLVM sources, use git pull: > > git pull llvm-upstream That should probably be either git pull or git pull llvm-upstream master since the first is shorter and works if llvm-upstream is the upstream for the

...isabled on the llvm bugzilla. > > We sometime lose edges during IfConversion of diamonds and it’s not > obvious how to reproduce on an upstream target. The documentation for > HasFallThrough says *may* fallthrough which I interpret as “this will be > true whenever we aren’t sure” but IfConverter::AnalyzeBranches() contains > the code: > > BBI.HasFallThrough = BBI.IsBrAnalyzable && BBI.FalseBB == nullptr; > BBI.HasFallThrough really means "Has Analyzable fallthrough." So this line is correct. > > So HasFallThrough is false whenever IsBrAnalyzable is fa...

Assume an architecture that has multiple condition code registers, e.g., powerpc. Now assume that there are predicate instructions like thumb2, but can specify which condition code register they refer to. Now also assume that these predicate instructions themselves are predicatible, if executed they change the current predication state. Can LLVM handle multiple levels of predication? When is

...vm/Support/raw_ostream.h" > > I'm working on release 3.1 though. > > hth, Daniel > > On 11/26/2012 03:00 PM, Bjorn De Sutter wrote: >> Hi, >> >> I am trying to debug my backend, and observe very strange behavior with dbgs(): >> >> In the IfConverter, I have added two debugging lines that print floating-point numbers for the sake of demonstration that such printing works fine. >> >> bool MeetIfcvtSizeLimit(MachineBasicBlock &BB, >> unsigned Cycle, unsigned Extra, >>...

FlyLanguage <flylanguage at gmail.com> writes: > 2) Nobody writing up how git should be used with the current llvm > workflow (which is not going to adapt to an SCM, but the other way > around, which is understandable.) Here is a first cut at that. Other git users, please chime in with suggestions, edits, etc. Non-git users, please ask for clarification where needed. This is

...9;m working on release 3.1 though. > > > > hth, Daniel > > > > On 11/26/2012 03:00 PM, Bjorn De Sutter wrote: > >> Hi, > >> > >> I am trying to debug my backend, and observe very strange behavior with > dbgs(): > >> > >> In the IfConverter, I have added two debugging lines that print > floating-point numbers for the sake of demonstration that such printing > works fine. > >> > >> bool MeetIfcvtSizeLimit(MachineBasicBlock &BB, > >> unsigned Cycle, unsigned Extra, > &g...

...ual corresponding basic block starting addresses. Could I use llvm to do this? From what I understand this issued is unrelevant with IR. Maybe I could get something from the machine code (MC). Perhaps I have to write a pass for llvm backend. Maybe I could get this information from BranchFolder and IfConverter machine function passes: http://llvm.org/docs/WritingAnLLVMBackend.html#branch-folding-and-if-conversion but I am not sure. I am new to llvm so I need some help, Thank you, -- Thanasis Petsas Distributed Computing Systems (DCS) Institute of Computer Science (ICS/FORTH) Heraklion, Crete Greece (...

Hi, I am trying to debug my backend, and observe very strange behavior with dbgs(): In the IfConverter, I have added two debugging lines that print floating-point numbers for the sake of demonstration that such printing works fine. bool MeetIfcvtSizeLimit(MachineBasicBlock &BB, unsigned Cycle, unsigned Extra, const BranchProbability &...

Hello! The if-converter tries to match 'Simple' patterns looking like this: // Simple (split, no rejoin): // EBB // | \_ // | | // | TBB---> exit // | // FBB The IfConverter::ValidSimple method (lib/CodeGen/IfConversion.cpp:461) checks if TBB matches this pattern. It basically does this by simply checking if AnalyseBranch fails on that block (IfConversion.cpp:640). This fails if TBB contains something that AnalyseBranch is not able to understand but is still a bran...

On 08/22/2011 09:37 PM, David A. Greene wrote: > FlyLanguage<flylanguage at gmail.com> writes: > >> > 2) Nobody writing up how git should be used with the current llvm >> > workflow (which is not going to adapt to an SCM, but the other way >> > around, which is understandable.) > Here is a first cut at that. Other git users, please chime in with >

...I'm working on release 3.1 though. > > > > hth, Daniel > > > > On 11/26/2012 03:00 PM, Bjorn De Sutter wrote: > >> Hi, > >> > >> I am trying to debug my backend, and observe very strange behavior with dbgs(): > >> > >> In the IfConverter, I have added two debugging lines that print floating-point numbers for the sake of demonstration that such printing works fine. > >> > >> bool MeetIfcvtSizeLimit(MachineBasicBlock &BB, > >> unsigned Cycle, unsigned Extra, > >>...

> On Aug 18, 2011, at 10:57 AM, David Greene wrote: >> >> Did the project ever come to a decision about making a transition to >> git? I'm trying to do some longer-term planning and it would be helpful >> to know what the roadmap is. It's stuck on: 1) A misunderstanding that global revision numbers are necessary and that 'git describe' along with

...quite right, and this pessimizes later transformations. Specifically, the issue is that BB#1 still lists BB#3 as a successor, but this is not true. Looking at IfConversion.cpp, I see this function: /// RemoveExtraEdges - Remove true / false edges if either / both are no longer /// successors. void IfConverter::RemoveExtraEdges(BBInfo &BBI) { MachineBasicBlock *TBB = NULL, *FBB = NULL; SmallVector<MachineOperand, 4> Cond; if (!TII->AnalyzeBranch(*BBI.BB, TBB, FBB, Cond)) BBI.BB->CorrectExtraCFGEdges(TBB, FBB, !Cond.empty()); } and I think that this function is supposed to clean...

Hi all, I got a silly bug when compiling our project with the latest Clang. Here's the outputted assembly: > tst r3, #255 > strbeq r6, [r7] > ldreq r6, [r4, r6, lsl #2] > strne r6, [r7, #4] > ldr r6, [r4, r6, lsl #2] > bx r6 For the code to execute correctly, either the _ldr_ should be a _ldrne_ instruction or the _ldreq_ instruction should be removed. The error seems to

On 5/12/11 11:46 AM, Arushi Aggarwal wrote: > I tried > llc -load /localhome/aggarwa4/llvm27/llvm-obj/projects/poolalloc/Debug/lib/libCodegen.so > --help > > But this does not show my pass. It says it is an unknown command line argument. I'm assuming you've looked at other MachineFunctionPass'es and have registered yours in the same way that they do. I don't think

Hi All, How can I run the IfConversion pass in JIT to optimize my code for ARM as a Target Architecture? -- View this message in context: http://llvm.1065342.n5.nabble.com/Machine-level-IfConversion-for-ARM-tp69513.html Sent from the LLVM - Dev mailing list archive at Nabble.com.

Tobias Grosser <tobias at grosser.es> writes: >> Sending Patches for Review >> -------------------------- >> >> git includes a whole set of tools for managing the patch review >> process. We kick things off with git format-patch: >> >> git format-patch -o $HOME/patches/ifconvert --thread --src-prefix=old/ \ >>

I tried llc -load /localhome/aggarwa4/llvm27/llvm-obj/projects/poolalloc/Debug/lib/libCodegen.so --help But this does not show my pass. It says it is an unknown command line argument. Arushi On Thu, May 12, 2011 at 11:21 AM, John Criswell <criswell at illinois.edu> wrote: > On 5/12/11 11:17 AM, Arushi Aggarwal wrote: >> >> What is the correct way to register/run a machine

On Tue, Oct 10, 2017 at 4:48 PM, Friedman, Eli via llvm-dev < llvm-dev at lists.llvm.org> wrote: > On 10/9/2017 3:10 AM, Gaël Jobin via llvm-dev wrote: > > Hi all, > > I got a silly bug when compiling our project with the latest Clang. Here's > the outputted assembly: > > tst r3, #255 > strbeq r6, [r7] > ldreq r6, [r4, r6, lsl #2] > strne r6, [r7, #4]