Displaying 5 results from an estimated 5 matches for "if_cond".
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idcond
2009 Feb 11
2
[LLVMdev] Eliminate PHI for non-copyable registers
In my hardware there are two special registers cannot be copied but can only
be assigned and referenced (read) in the other instruction. They are
allocatable also.
br i1 %if_cond, label %then, label %else
then:
%x1 = fptosi float %y1 to i32
br label %endif
else:
%x2 = fptosi float %y2 to i32
br label %endif
endif:
%x3 = phi i32 [%x1, %then], [%x2, %else]
PNE::LowerAtomiPHINode() fails because TargetInstrInfo::copyRegToReg()
doesn't support the copy of this ty...
2009 Jun 21
0
[PATCH] nv50: initial support for IF, ELSE, ENDIF insns
...0,8 @@ struct nv50_reg {
int acc; /* instruction where this reg is last read (first insn == 1) */
};
+#define MAX_IF_LEVEL 4 /* arbitrary value */
+
struct nv50_pc {
struct nv50_program *p;
@@ -119,11 +121,17 @@ struct nv50_pc {
struct nv50_reg r_hpos[4];
+ struct nv50_program_exec *if_cond;
+ struct nv50_program_exec *if_insn[MAX_IF_LEVEL];
+ struct nv50_program_exec *if_join[MAX_IF_LEVEL];
+ unsigned if_lvl;
+
/* current instruction and total number of insns */
unsigned insn_cur;
unsigned insn_nr;
boolean allow32;
+ boolean join_on;
};
static inline void
@@ -208,22 +21...
2009 Feb 12
0
[LLVMdev] Eliminate PHI for non-copyable registers
On Feb 11, 2009, at 4:07 AM, Alex wrote:
> In my hardware there are two special registers cannot be copied but
> can only be assigned and referenced (read) in the other instruction.
> They are allocatable also.
>
> br i1 %if_cond, label %then, label %else
> then:
> %x1 = fptosi float %y1 to i32
> br label %endif
> else:
> %x2 = fptosi float %y2 to i32
> br label %endif
> endif:
> %x3 = phi i32 [%x1, %then], [%x2, %else]
>
> PNE::LowerAtomiPHINode() fails because
> TargetInstrInfo...
2009 Feb 12
2
[LLVMdev] Eliminate PHI for non-copyable registers
...attner-2 wrote:
>
>
> On Feb 11, 2009, at 4:07 AM, Alex wrote:
>
>> In my hardware there are two special registers cannot be copied but
>> can only be assigned and referenced (read) in the other instruction.
>> They are allocatable also.
>>
>> br i1 %if_cond, label %then, label %else
>> then:
>> %x1 = fptosi float %y1 to i32
>> br label %endif
>> else:
>> %x2 = fptosi float %y2 to i32
>> br label %endif
>> endif:
>> %x3 = phi i32 [%x1, %then], [%x2, %else]
>>
>> PNE::LowerAtomiPHINod...
2009 Jun 21
0
[PATCH] nv50: support for SLE, SNE, SEQ, SGT
...nst[0] |= 0x000001fc;
+ e->inst[1] |= 0x00000008;
+ }
+
set_src_0(pc, src0, e);
set_src_1(pc, src1, e);
- emit(pc, e);
- /* cvt.f32.u32 */
- e = exec(pc);
- e->inst[0] = 0xa0000001;
- e->inst[1] = 0x64014780;
- set_dst(pc, rdst, e);
- set_src_0(pc, dst, e);
emit(pc, e);
-
pc->if_cond = e;
- if (dst != rdst)
- free_temp(pc, dst);
+ if (rdst)
+ emit_cvt(pc, rdst, -1, dst, CVTOP_ABSRN, CVT_F32_S32);
}
static INLINE void
emit_flr(struct nv50_pc *pc, struct nv50_reg *dst, struct nv50_reg *src)
{
- emit_cvt(pc, dst, src, -1, CVTOP_FLOOR, CVT_F32_F32_ROP);
+ emit_cvt(pc, dst...