Displaying 1 result from an estimated 1 matches for "iec_rsv0".
2013 Sep 26
1
[LLVMdev] [llvm] r190717 - Adds support for Atom Silvermont (SLM) - -march=slm
...-march=slm
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> On Sep 13, 2013, at 1:26 PM, Hal Finkel <hfinkel at anl.gov> wrote:
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>> ----- Original Message -----
>>>
>>>
>>> Just out of curiosity, when you have this:
>>> + InstrItinData<IIC_SHD16_REG_IM, [InstrStage<2, [IEC_RSV0]>] >,
>>>
>>> do you intend this to mean that the shift occupied the IEC_RSV0
>>> unit, and nothing else can use it for 2 cycles? Or you do mean that
>>> the latency is 2 cycles, but you can still issue back-to-back
>>> independent shifts?
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