Displaying 3 results from an estimated 3 matches for "idx3".
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2001 Mar 04
1
bubblebabble patch
...gned int rounds, idx, retval_idx, seed;
+ char *retval;
+
+ rounds = (dgst_raw_len / 2) + 1;
+
+ retval = xmalloc(sizeof(char)*(rounds*6));
+
+ seed = 1;
+
+ retval_idx = 0;
+
+ retval[retval_idx++] = 'x';
+
+ for (idx=0;idx<rounds;idx++) {
+
+ unsigned int idx0, idx1, idx2, idx3, idx4;
+
+ if ((idx + 1 < rounds) || (dgst_raw_len % 2 != 0)) {
+
+ idx0 = (((((unsigned int)(dgst_raw[2*idx])) >> 6) & 3) + seed) % 6;
+ idx1 = (((unsigned int)(dgst_raw[2*idx])) >> 2) & 15;
+ idx2 = ((((unsigned int)(dgst_raw[2*idx])) & 3) + (seed / 6)) % 6;
+
+...
2003 Feb 21
2
how to chage values in data frame to NA iside a function
Dear all
I have a function in which I would like to change some values to NA according to
some condition.
dropout<-function(y, nahr=FALSE,...) {
<some stuff for computing an index>
if (nahr) y[index]<<-NA
invisible(index)
}
in case y is a vector all works OK but if it is a part of data frame by calling
dropout(df$y) or dropout(df[,number]) no change is done.
Please can you
2016 Aug 23
2
How to describe the RegisterInfo?
Yes, the arch is just as you said, something like AMD GPU, but Intel GPU
don't have separate register file for 'scalar/vector'.
In fact my idea of defining the register tuples was borrowed from
SIRegisterInfo.td in AMD GPU.
But seems that AMD GPU mainly support i32/i64 register type, while Intel
GPU also support byte/short register type.
So I have to start defining the registers from