search for: idts

Dear members, I am extracting a pdf table by the following code: > library(tabulizer) > IDT <- extract_tables("https://www.canmoney.in/pdf/INTRADAYLEVERAGE-20220531-latest.pdf",output = "data.frame") It returns 4 different data frames which I want to combine them and make one data frame. But when I run this: >

Clearly the column names are different. You need to decide what to do about that. Choose the subset of dataframes where the column names are the same? Rename columns? Omit some columns? Add missing columns filled with NA? On April 9, 2023 10:22:32 AM PDT, akshay kulkarni <akshay_e4 at hotmail.com> wrote: >Dear members, > I am extracting a pdf table by the

...- arch/x86/kernel/idt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/idt.c b/arch/x86/kernel/idt.c index 87ef69a72c52..7f81c1294847 100644 --- a/arch/x86/kernel/idt.c +++ b/arch/x86/kernel/idt.c @@ -166,7 +166,7 @@ static const __initconst struct idt_data dbg_idts[] = { #endif /* Must be page-aligned because the real IDT is used in a fixmap. */ -gate_desc idt_table[IDT_ENTRIES] __page_aligned_bss; +gate_desc idt_table[IDT_ENTRIES] __page_aligned_data; struct desc_ptr idt_descr __ro_after_init = { .size = (IDT_ENTRIES * 2 * sizeof(unsigned long)) -...

...arch/x86/kernel/idt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/x86/kernel/idt.c b/arch/x86/kernel/idt.c index 0db21206f2f3..b920f2352df5 100644 --- a/arch/x86/kernel/idt.c +++ b/arch/x86/kernel/idt.c @@ -158,7 +158,7 @@ static const __initconst struct idt_data apic_idts[] = { }; /* Must be page-aligned because the real IDT is used in the cpu entry area */ -static gate_desc idt_table[IDT_ENTRIES] __page_aligned_bss; +static gate_desc idt_table[IDT_ENTRIES] __page_aligned_data; struct desc_ptr idt_descr __ro_after_init = { .size = IDT_TABLE_SIZE - 1, -- 2...

From: Joerg Roedel <jroedel at suse.de> Move these two functions from kernel/idt.c to include/asm/desc.h: * init_idt_data() * idt_init_desc() These functions are needed to setup IDT entries very early and need to be called from head64.c. To be usable this early these functions need to be compiled without instrumentation and the stack-protector feature. These features need to be kept

Dear Jeff, Thanks for your reply. I have the following: > colnames(IDT[[4]]) [1] "X168" "TATA.MOTORS.LIMITED" "TATAMOTORS" "X4" THe above has to be the first row of IDT[[4]]. The first row is getting parsed as the column name. How do you make that the first row of IDT[[4]]? Thanking you, Yours sincerely,

This makes the IDT unconditionally read-only. This primarily removes the IDT from being a target for arbitrary memory write attacks. It has an added benefit of also not leaking (via the "sidt" instruction) the kernel base offset, if it has been relocated. Signed-off-by: Kees Cook <keescook at chromium.org> Cc: Eric Northup <digitaleric at google.com> ---

This makes the IDT unconditionally read-only. This primarily removes the IDT from being a target for arbitrary memory write attacks. It has an added benefit of also not leaking (via the "sidt" instruction) the kernel base offset, if it has been relocated. Signed-off-by: Kees Cook <keescook at chromium.org> Cc: Eric Northup <digitaleric at google.com> ---

Dear all, I am quite new to R; facing certain problems: Say, I have a text file( named as "try"): Year C1 C2 C3 C4 C5 C6 Y1 3.5 13.8 9.5 6.8 0.4 24.2 Y2 3.8 13.9 9.9 7.6 0.7 12.8 Y3 4.5 14.5 14.2 9.2 0.6 14.5 Y4 5.9 16.2 24.6 12.7 0.2 24.3 Y5 7.2 20.4 40.6 18.2 0.8 28.2 Y6 5.9 18.6 37.4 14.5 0.3 36.9 Y7 8.0 16.1 88.6 24.1 0.1 34.6 Y8 13.6 21.1 56.3 19.0 0.7 33.3 I wish to import the

On Tue, Feb 11, 2020 at 5:53 AM Joerg Roedel <joro at 8bytes.org> wrote: > > From: Joerg Roedel <jroedel at suse.de> > > With SEV-ES, exception handling is needed very early, even before the > kernel has cleared the bss segment. In order to prevent clearing the > currently used IDT, move the IDT to the data segment. Ugh. At the very least this needs a comment in the

On Tue, Feb 11, 2020 at 5:53 AM Joerg Roedel <joro at 8bytes.org> wrote: > > From: Joerg Roedel <jroedel at suse.de> > > With SEV-ES, exception handling is needed very early, even before the > kernel has cleared the bss segment. In order to prevent clearing the > currently used IDT, move the IDT to the data segment. Ugh. At the very least this needs a comment in the

From: Joerg Roedel <jroedel at suse.de> Load the IDT right after switching to virtual addresses in head_64.S so that the kernel can handle #VC exceptions. Signed-off-by: Joerg Roedel <jroedel at suse.de> Link: https://lore.kernel.org/r/20200724160336.5435-36-joro at 8bytes.org --- arch/x86/include/asm/setup.h | 3 +++ arch/x86/kernel/head64.c | 3 +++ arch/x86/kernel/head_64.S

Dear Jeff, I want to rbind. Thanking you, Yours sincerely, AKSHAY M KULKARNI ________________________________ From: R-help <r-help-bounces at r-project.org> on behalf of Jeff Newmiller <jdnewmil at dcn.davis.ca.us> Sent: Sunday, April 9, 2023 11:57 PM To: r-help at r-project.org <r-help at r-project.org> Subject: Re: [R] extracting pdf tables... Sorry, did not

> On Feb 12, 2020, at 3:55 AM, Joerg Roedel <joro at 8bytes.org> wrote: > > ?On Tue, Feb 11, 2020 at 02:41:25PM -0800, Andy Lutomirski wrote: >>> On Tue, Feb 11, 2020 at 5:53 AM Joerg Roedel <joro at 8bytes.org> wrote: >>> >>> From: Joerg Roedel <jroedel at suse.de> >>> >>> With SEV-ES, exception handling is needed very

> On Feb 12, 2020, at 3:55 AM, Joerg Roedel <joro at 8bytes.org> wrote: > > ?On Tue, Feb 11, 2020 at 02:41:25PM -0800, Andy Lutomirski wrote: >>> On Tue, Feb 11, 2020 at 5:53 AM Joerg Roedel <joro at 8bytes.org> wrote: >>> >>> From: Joerg Roedel <jroedel at suse.de> >>> >>> With SEV-ES, exception handling is needed very

Make a copy of the IDT (as seen via the "sidt" instruction) read-only. This primarily removes the IDT from being a target for arbitrary memory write attacks, and has the added benefit of also not leaking the kernel base offset, if it has been relocated. We already did this on vendor == Intel and family == 5 because of the F0 0F bug -- regardless of if a particular CPU had the F0 0F bug

Make a copy of the IDT (as seen via the "sidt" instruction) read-only. This primarily removes the IDT from being a target for arbitrary memory write attacks, and has the added benefit of also not leaking the kernel base offset, if it has been relocated. We already did this on vendor == Intel and family == 5 because of the F0 0F bug -- regardless of if a particular CPU had the F0 0F bug

From: Joerg Roedel <jroedel at suse.de> Setup an early handler for #VC exceptions. There is no GHCB mapped yet, so just re-use the vc_no_ghcb_handler. It can only handle CPUID exit-codes, but that should be enough to get the kernel through verify_cpu() and __startup_64() until it runs on virtual addresses. Signed-off-by: Joerg Roedel <jroedel at suse.de> Link:

On Tue, Feb 11, 2020 at 02:41:25PM -0800, Andy Lutomirski wrote: > On Tue, Feb 11, 2020 at 5:53 AM Joerg Roedel <joro at 8bytes.org> wrote: > > > > From: Joerg Roedel <jroedel at suse.de> > > > > With SEV-ES, exception handling is needed very early, even before the > > kernel has cleared the bss segment. In order to prevent clearing the > >

On 12.02.20 17:23, Andy Lutomirski wrote: > > >> On Feb 12, 2020, at 3:55 AM, Joerg Roedel <joro at 8bytes.org> wrote: >> >> ?On Tue, Feb 11, 2020 at 02:41:25PM -0800, Andy Lutomirski wrote: >>>> On Tue, Feb 11, 2020 at 5:53 AM Joerg Roedel <joro at 8bytes.org> wrote: >>>> >>>> From: Joerg Roedel <jroedel at suse.de>