Displaying 16 results from an estimated 16 matches for "idt_init_desc".
2020 Jul 14
0
[PATCH v4 29/75] x86/idt: Move two function from k/idt.c to i/a/desc.h
From: Joerg Roedel <jroedel at suse.de>
Move these two functions from kernel/idt.c to include/asm/desc.h:
* init_idt_data()
* idt_init_desc()
These functions are needed to setup IDT entries very early and need to
be called from head64.c. To be usable this early these functions need to
be compiled without instrumentation and the stack-protector feature.
These features need to be kept enabled for kernel/idt.c, so head64.c
must use its o...
2020 Aug 31
2
[PATCH v6 42/76] x86/sev-es: Setup early #VC handler
On Mon, Aug 24, 2020 at 10:54:37AM +0200, Joerg Roedel wrote:
> +#ifdef CONFIG_AMD_MEM_ENCRYPT
> +static void set_early_idt_handler(gate_desc *idt, int n, void *handler)
> +{
> + struct idt_data data;
> + gate_desc desc;
> +
> + init_idt_data(&data, n, handler);
> + idt_init_desc(&desc, &data);
> + native_write_idt_entry(idt, n, &desc);
> +}
> +#endif
> +
> +static struct desc_ptr early_idt_descr __initdata = {
> + .size = IDT_TABLE_SIZE - 1,
> + .address = 0 /* Needs physical address of idt_table - initialized at runtime. */,
> +};
>...
2020 Aug 31
2
[PATCH v6 42/76] x86/sev-es: Setup early #VC handler
On Mon, Aug 24, 2020 at 10:54:37AM +0200, Joerg Roedel wrote:
> +#ifdef CONFIG_AMD_MEM_ENCRYPT
> +static void set_early_idt_handler(gate_desc *idt, int n, void *handler)
> +{
> + struct idt_data data;
> + gate_desc desc;
> +
> + init_idt_data(&data, n, handler);
> + idt_init_desc(&desc, &data);
> + native_write_idt_entry(idt, n, &desc);
> +}
> +#endif
> +
> +static struct desc_ptr early_idt_descr __initdata = {
> + .size = IDT_TABLE_SIZE - 1,
> + .address = 0 /* Needs physical address of idt_table - initialized at runtime. */,
> +};
>...
2020 Sep 07
0
[PATCH v7 39/72] x86/sev-es: Setup early #VC handler
...early on.
@@ -540,10 +541,29 @@ static struct desc_ptr bringup_idt_descr = {
.address = 0, /* Set at runtime */
};
+#ifdef CONFIG_AMD_MEM_ENCRYPT
+static void set_bringup_idt_handler(int n, void *handler)
+{
+ struct idt_data data;
+ gate_desc desc;
+
+ init_idt_data(&data, n, handler);
+ idt_init_desc(&desc, &data);
+ native_write_idt_entry(bringup_idt_table, n, &desc);
+}
+#endif
+
/* This runs while still in the direct mapping */
static void startup_64_load_idt(unsigned long physbase)
{
struct desc_ptr *desc = fixup_pointer(&bringup_idt_descr, physbase);
+ void __maybe_unu...
2020 Aug 24
0
[PATCH v6 36/76] x86/head/64: Load IDT earlier
...__init early_idt_setup_early_handler(unsigned long physaddr)
+{
+ gate_desc *idt;
+ int i;
+
+ idt = fixup_pointer(idt_table, physaddr);
+
+ for (i = 0; i < NUM_EXCEPTION_VECTORS; i++) {
+ struct idt_data data;
+ gate_desc desc;
+
+ init_idt_data(&data, i, early_idt_handler_array[i]);
+ idt_init_desc(&desc, &data);
+ native_write_idt_entry(idt, i, &desc);
+ }
+}
+
+void early_load_idt(void)
+{
+ load_idt(&idt_descr);
+}
--
2.28.0
2020 Aug 24
0
[PATCH v6 42/76] x86/sev-es: Setup early #VC handler
...unsigned int vector;
@@ -408,3 +409,38 @@ void early_load_idt(void)
{
load_idt(&idt_descr);
}
+
+#ifdef CONFIG_AMD_MEM_ENCRYPT
+static void set_early_idt_handler(gate_desc *idt, int n, void *handler)
+{
+ struct idt_data data;
+ gate_desc desc;
+
+ init_idt_data(&data, n, handler);
+ idt_init_desc(&desc, &data);
+ native_write_idt_entry(idt, n, &desc);
+}
+#endif
+
+static struct desc_ptr early_idt_descr __initdata = {
+ .size = IDT_TABLE_SIZE - 1,
+ .address = 0 /* Needs physical address of idt_table - initialized at runtime. */,
+};
+
+void __init early_idt_setup(unsigned long...
2020 Jul 14
92
[PATCH v4 00/75] x86: SEV-ES Guest Support
From: Joerg Roedel <jroedel at suse.de>
Hi,
here is the fourth version of the SEV-ES Guest Support patches. I
addressed the review comments sent to me for the previous version and
rebased the code v5.8-rc5.
The biggest change in this version is the IST handling code for the
#VC handler. I adapted the entry code for the #VC handler to the big
pile of entry code changes merged into
2020 Jul 14
92
[PATCH v4 00/75] x86: SEV-ES Guest Support
From: Joerg Roedel <jroedel at suse.de>
Hi,
here is the fourth version of the SEV-ES Guest Support patches. I
addressed the review comments sent to me for the previous version and
rebased the code v5.8-rc5.
The biggest change in this version is the IST handling code for the
#VC handler. I adapted the entry code for the #VC handler to the big
pile of entry code changes merged into
2020 Sep 07
84
[PATCH v7 00/72] x86: SEV-ES Guest Support
From: Joerg Roedel <jroedel at suse.de>
Hi,
here is a new version of the SEV-ES Guest Support patches for x86. The
previous versions can be found as a linked list starting here:
https://lore.kernel.org/lkml/20200824085511.7553-1-joro at 8bytes.org/
I updated the patch-set based on ther review comments I got and the
discussions around it.
Another important change is that the early IDT
2020 Sep 07
84
[PATCH v7 00/72] x86: SEV-ES Guest Support
From: Joerg Roedel <jroedel at suse.de>
Hi,
here is a new version of the SEV-ES Guest Support patches for x86. The
previous versions can be found as a linked list starting here:
https://lore.kernel.org/lkml/20200824085511.7553-1-joro at 8bytes.org/
I updated the patch-set based on ther review comments I got and the
discussions around it.
Another important change is that the early IDT
2020 Apr 28
116
[PATCH v3 00/75] x86: SEV-ES Guest Support
Hi,
here is the next version of changes to enable Linux to run as an SEV-ES
guest. The code was rebased to v5.7-rc3 and got a fair number of changes
since the last version.
What is SEV-ES
==============
SEV-ES is an acronym for 'Secure Encrypted Virtualization - Encrypted
State' and means a hardware feature of AMD processors which hides the
register state of VCPUs to the hypervisor by
2020 Apr 28
116
[PATCH v3 00/75] x86: SEV-ES Guest Support
Hi,
here is the next version of changes to enable Linux to run as an SEV-ES
guest. The code was rebased to v5.7-rc3 and got a fair number of changes
since the last version.
What is SEV-ES
==============
SEV-ES is an acronym for 'Secure Encrypted Virtualization - Encrypted
State' and means a hardware feature of AMD processors which hides the
register state of VCPUs to the hypervisor by
2020 Aug 24
96
[PATCH v6 00/76] x86: SEV-ES Guest Support
From: Joerg Roedel <jroedel at suse.de>
Hi,
here is the new version of the SEV-ES client enabling patch-set. It is
based on the latest tip/master branch and contains the necessary
changes. In particular those ar:
- Enabling CR4.FSGSBASE early on supported processors so that
early #VC exceptions on APs can be handled.
- Add another patch (patch 1) to fix a KVM frame-size build
2020 Feb 11
83
[RFC PATCH 00/62] Linux as SEV-ES Guest Support
Hi,
here is the first public post of the patch-set to enable Linux to run
under SEV-ES enabled hypervisors. The code is mostly feature-complete,
but there are still a couple of bugs to fix. Nevertheless, given the
size of the patch-set, I think it is about time to ask for initial
feedback of the changes that come with it. To better understand the code
here is a quick explanation of SEV-ES first.
2020 Feb 11
83
[RFC PATCH 00/62] Linux as SEV-ES Guest Support
Hi,
here is the first public post of the patch-set to enable Linux to run
under SEV-ES enabled hypervisors. The code is mostly feature-complete,
but there are still a couple of bugs to fix. Nevertheless, given the
size of the patch-set, I think it is about time to ask for initial
feedback of the changes that come with it. To better understand the code
here is a quick explanation of SEV-ES first.
2020 Jul 24
86
[PATCH v5 00/75] x86: SEV-ES Guest Support
From: Joerg Roedel <jroedel at suse.de>
Hi,
here is a rebased version of the latest SEV-ES patches. They are now
based on latest tip/master instead of upstream Linux and include the
necessary changes.
Changes to v4 are in particular:
- Moved early IDT setup code to idt.c, because the idt_descr
and the idt_table are now static
- This required to make stack protector work early (or