search for: idle_pg_t

Hello, This series has been split into two patches, one for arm and one for x86. I figured that this was easier than doing it as a single combined patch, especially as the changes are functionally independent. x86 has been boot tested, but arm has not even been compile tested as I lack a suitable cross compiler. However, the changes are just text replacement, so I dont expect any issues. The

...de <linux/linkage.h> #include <asm/segment.h> +#else +#include <xen/config.h> +#include <asm/asm_defns.h> +#endif #include <asm/page.h> # @@ -56,7 +61,11 @@ 1: 1: # set up page table +#ifndef __XEN__ movl $swsusp_pg_dir-__PAGE_OFFSET, %eax +#else + movl $idle_pg_table-__PAGE_OFFSET, %eax +#endif movl %eax, %cr3 testl $1, real_efer_save_restore - wakeup_code @@ -88,7 +97,11 @@ 1: cmpl $0x12345678, %eax jne bogus_real_magic +#ifndef __XEN__ ljmpl $__KERNEL_CS,$wakeup_pmode_return +#else + ljmpl $(__HYPERVISOR_CS),$wakeup_pmode_return +#endif...

While adding code to create the compatibility p2m table mappings it seemed to me that the creation of the native ones is restricted to memory below the 512G boundary - otherwise, additional L2 tables would need to be allocated (currently other memory following the one L2 page getting allocated would be blindly overwritten). While I realize that machines this big aren''t likely to be

Hello! I have a slight problem in my guest port with the WP bit in CR0. The original kernel maps certain kernel pages to user-mode read-only and relies on the kernel being able to modify these despite the read-only bit being set in the pages. This in turn requires that the WP bit is unset in CR0. Unfortunately, Xen doesn''t allow the WP bit to be zeroed because Xen wants to share pages

..._saved_magic + + /* fpu init? */ + + /* Initialise CR4. */ +#if CONFIG_PAGING_LEVELS == 2 + mov $X86_CR4_PSE, %ecx +#else + mov $X86_CR4_PAE, %ecx +#endif + mov %ecx, %cr4 + + /* Load pagetable base register */ + mov $sym_phys(idle_pg_table),%eax + add bootsym_phys(trampoline_xen_phys_start),%eax + mov %eax,%cr3 + + /* Will cpuid feature change after resume? */ +#if CONFIG_PAGING_LEVELS != 2 + /* Set up EFER (Extended Feature Enable Register). */ + mov bootsym_phys(cpuid_ext_features)...