Displaying 3 results from an estimated 3 matches for "idctslow".
2006 May 31
0
Theora Decoding on FPGA
...http://atlas.lsc.ic.unicamp.br/~portavales/wp-content/uploads/2006/05/soc_proposal.txt
There is also a presentation with a better division of the hardware modules:
http://svn.xiph.org/trunk/theora-fpga/doc/hard_theora.pdf
Now, I'm working on it, and today I did a simple implementation of the
IDctSlow procedure as a VHDL module.
This module run and decode samples correctly, but It consumes a lot of
FPGA resources (logic cells, multipliers, etc..)
I will optimize this module for area, to get better results.
The testbench uses the GHDL tool to simulate and can be download from the svn:
http://s...
2006 Jun 05
0
Idct - fpga - improved
...lls.
And the clock frequency from 30 Mhz to 90 Mhz.
Now I'm improving the latency of samples (number of clock cycles
needed to decode a data sample).
Report:
--------------
Fitter Status : Successful - Mon Jun 5 16:38:21 2006
Quartus II Version : 5.1 Build 176 10/26/2005 SJ
Revision Name : idctslow
Top-level Entity Name : IDctSlow
Family : Stratix II
Device : EP2S60F672C5ES
Timing Models : Final
Total ALUTs : 2,538 / 48,352 ( 5 % )
Total registers : 466
Total pins : 54 / 493 ( 11 % )
Total virtual pins : 0
Total memory bits : 3,072 / 2,544,192 ( < 1 % )
DSP block 9-bit elements : 2 / 288 (...
2006 May 30
2
16 bits, cast on idct function
Hi all,
Just a stupid question
The IDctSlow function on file idct.c has this line :
ip[0] = (ogg_int16_t)((_Gd + _Cd ) >> 0);
The ip[0] , _Gd and _Cd are of type ogg_int32_t
My question is:
The result of (_Gd + _Cd) can be a number with more than 16 bits ?
(yes, it can be because they are int32, but the algorithm could
gu...