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A naive question from someone who knows nothing of icmd or bundles... Would it be better to wait for both bits to become 0 (I.e. 0x6)? On Jun 8, 2015 11:54 AM, "Alexandre Courbot" <acourbot at nvidia.com> wrote: > When emitting the ICMD bundle, wait on the bottom half (bit 3 of the > GR_STATUS register) instead of upper half (bit...

On Mon, Jun 8, 2015 at 10:43 PM, Alexandre Courbot <gnurou at gmail.com> wrote: > On Mon, Jun 8, 2015 at 8:04 PM, Ilia Mirkin <imirkin at alum.mit.edu> wrote: >> A naive question from someone who knows nothing of icmd or bundles... Would >> it be better to wait for both bits to become 0 (I.e. 0x6)? > > My understanding is that a method reaching the bottom half implies it > has passed to upper half (whatever these halfs are, I need to dig into > the doc to completely figure it out), and thus tha...

Here are a few small fixes for issues we found while implementing support for GM20B. The first two are specific to Tegra/GK20A, but the last 3 patches may have a broader (hopefully beneficial) effect. Note that the newly introduced gf100_gr_wait_idle() function on patch 5/5 is exported on purpose. GK20A and GM20B drivers will soon make use of it. Ben, since you seemed to like these changes, a

...ctx_oclass; extern struct nvc0_graph_init *nvc0_grctx_init_hub[]; extern struct nvc0_graph_init nvc0_grctx_init_base[]; @@ -237,12 +239,17 @@ extern struct nvc0_graph_init nvc0_grctx_init_gpc_1[]; extern struct nvc0_graph_init nvc0_grctx_init_tpc[]; extern struct nvc0_graph_init nvc0_grctx_init_icmd[]; extern struct nvc0_graph_init nvd9_grctx_init_icmd[]; // +extern struct nvc0_graph_init nve4_grctx_init_icmd[]; + +extern struct nvc0_graph_init *nve4_grctx_init_hub[]; +extern struct nvc0_graph_init *nve4_grctx_init_gpc[]; extern struct nvc0_graph_mthd nvc0_grctx_init_mthd[]; extern struct...

...struct nvc0_graph_init *nvc0_grctx_init_hub[]; > extern struct nvc0_graph_init nvc0_grctx_init_base[]; > @@ -237,12 +239,17 @@ extern struct nvc0_graph_init nvc0_grctx_init_gpc_1[]; > extern struct nvc0_graph_init nvc0_grctx_init_tpc[]; > extern struct nvc0_graph_init nvc0_grctx_init_icmd[]; > extern struct nvc0_graph_init nvd9_grctx_init_icmd[]; // > +extern struct nvc0_graph_init nve4_grctx_init_icmd[]; > + > +extern struct nvc0_graph_init *nve4_grctx_init_hub[]; > +extern struct nvc0_graph_init *nve4_grctx_init_gpc[]; > > extern struct nvc0_graph_mthd nvc0_...

Hi everyone, Here is the second batch of patches to add GK20A support to Nouveau. This time we are adding the actual chip support, and this series brings the driver to a point where a slightly-tweaked Mesa successfully runs shaders and renders triangles on GBM! Many thanks to Thierry Reding and the people on the #nouveau IRC channel for their help without which we would not have reached this

Latest patches for GK20A, taking comments received for v3 into account. Changes since v3: - use only pfn_to_page() and page_to_pfn() in GK20A's FB. These functions are present on every arch and the physical address to page frame number conversion is also consistently a shift of PAGE_SHIFT. This part will probably be replaced by something nicer in the future anyway. - fixed a warning on

Hi everyone, Way overdue v2 of the final patches that enable basic GK20A support. Hopefully all the issues raised with v1 have been addressed. Changes since v1: - Use gk20a clock driver by Ben instead of twiddling nv04's - Name new classes after gk20a instead of nvea - Addressed comments about BAR initialization code factorization - Removed non-essential code which only purpose was to avoid

...h of register address/value pairs anyway The new firmware files introduced are: nvidia/gk20a/sw_nonctx.bin (gr_pack_mmio) nvidia/gk20a/sw_ctx.bin (grctx_pack_hub, grctx_pack_gpc, grctx_pack_zcull, grctx_pack_tpc, grctx_pack_ppc) nvidia/gk20a/sw_bundle_init.bin (grctx_pack_icmd) nvidia/gk20a/sw_method_init.bin (grctx_pack_mthd) Third patch is trivial and adds the GM20B FIFO device. Fourth patch adds GM20B GR based on the reworked GK20A support. GM20B will rely on the same firmware files as GK20A (also clean for release). Note that this is not full support yet for releas...

...h of register address/value pairs anyway The new firmware files introduced are: nvidia/gk20a/sw_nonctx.bin (gr_pack_mmio) nvidia/gk20a/sw_ctx.bin (grctx_pack_hub, grctx_pack_gpc, grctx_pack_zcull, grctx_pack_tpc, grctx_pack_ppc) nvidia/gk20a/sw_bundle_init.bin (grctx_pack_icmd) nvidia/gk20a/sw_method_init.bin (grctx_pack_mthd) Third patch is trivial and adds the GM20B FIFO device. Fourth patch adds GM20B GR based on the reworked GK20A support. GM20B will rely on the same firmware files as GK20A (also clean for release). Note that this is not full support yet for releas...

Changes since v2: - Enabled software class - Removed unneeded changes to nouveau_accel_init() - Replaced use of architecture-private pfn_to_dma() and dma_to_pfn() with the portable page_to_phys()/phys_to_page() - Fixed incorrect comment/commit log talking about bytes instead of words Hope this looks good! Once this gets merged the next set will be to use this driver on Jetson and Venice2