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valur
2013 Dec 20
1
[LLVMdev] extra one cycle of getOperandLatency
...after
instruction issue the values which correspond to specific operand indices
are defined or read.
I thought if an instruction reads the operands at the first cycle
and produces the result at the second cycle. InstrItinData should be written
in something like this,
InstrItinData<IIC_iALUr ,[InstrStage<1, [FU_x]>], [2, 1, 1]>
Therefore, for operand latency of iALUr output to iALUr input is latency
of "1". However, by the implementatoin of getOperandLatency, the latency
of such definition is latency of "2". That's not what I want.
After some diggin...