search for: i6s

Displaying 20 results from an estimated 105 matches for "i6s".

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2008 Mar 06
2
Help with parsing a data file
Hi All, I need to parse data from a file, example shown below. The first two lines can be skipped, the third line contains the column names. The next 13 lines can be skipped. The next line "1991" is a year value, with the following 13 values data for that year. The file then repeats this format with (year, 13 lines of data for that year). I would ideally like to end up with an
2017 Jul 28
2
arbitrary bit number
Hello, I wanted to ask one general question ( for now it is hard to check it manually, maybe there is a fast answer): can I construct an operation, say, addition, from operand_0 - 5 bits size and operand_1 - 3 bit size -> receive result as 6 bit size . I am basically reducing these sizes in the whole IR, so I want that all operands can have arbitrary sizes ( llvm pass is not really good because
2017 Sep 15
2
What should a truncating store do?
For example, truncating store of an i32 to i6. My assumption was that this should write the low six bits of the i32 to somewhere in memory. Should the top 24 bits of a corresponding 32 bit region of memory be unchanged, zero, undefined? Should the two bits that would round the i6 up to a byte be preserved, zero, undefined? I can't write six bits directly so am trying to determine what set
2011 Aug 31
2
[LLVMdev] A pass to minimize instruction bitwidth?
Does llvm have a pass that minimizes the bitwidth of llvm instructions? For instance:   %8 = and i32 %7, 63 63 is 111111 in binary. So the 'and' instruction only requires 6 bits. We could rewrite the above code as:   %8 = trunc i32 %7 to i6   %9 = and i6 %8, 63 Since we only need the lower 6 bits we could also propagate this change backwards to reduce the bitwidth of prior
2002 Mar 03
2
indexing data.frames
Dear R-help, I have a series of data.frames (i1,i2,...,in) all containing the same number of items, but dissimilar content. I would like to instal them in another data.frame, say index, so that I can access their items with index[i,j]. No matter how I try to set index up, its subframes cannot be indexed, because they all have the row number of 1. What am I doing wrong? (I get the same
2009 Aug 17
1
R : how does %in% operator work?
*Problem-1* CASE-I---------(works fine) > var1<-"tom" > var1 [1"tom" > var1<-as.character(var1) > var1 [1] "tom" > var2<-c("tom","harry","kate") > logc<-(var1 %in% var2) > logc [1] TRUE > typeof(var1) [1] "character" > typeof(var2) [1] "character"
2015 Jul 24
2
[LLVMdev] SIMD for sdiv <2 x i64>
It seems that that it's hard to vectorize int64 in LLVM. For example, LLVM 3.4 generates very complicated code for the following IR. I am running on a Haswell processor. Is it because there is no alternative AVX/2 instructions for int64? The same thing also happens to zext <2 x i32> -> <2 x i64> and trunc <2 x i64> -> <2 x i32>. Any ideas to optimize these
2010 Jun 09
1
counting across leves of factors
I have dataframe with 17factors variables (for example every factor have 3levels) I have maybe 5000 observation. And i need to do table where is in every raw 1 of possible combination of this factors and the numbur how many time is this combination in my dataset. I wrote one code, but this is very slow and dumb. it looks like this: i<-0 for(i1 in levels(hivdat$pohl)){
2004 Jun 06
0
strata() in clogit()
How can I get the log odds associated with the levels in strata() within a clogit() model? I'm running R-1.9.0 on a Linux platform. I am using clogit() to run a Rasch model in Item Response Theory in psychometrics. Symbolically, the model is: logit(p_{j,k}) = \log({\Pr(p_{j,k}) \over \Pr(1-p_{j,k})}) = \theta_j - \alpha_k, That is, the log odds of answering an test item correctly is
2017 Sep 15
0
What should a truncating store do?
On 9/15/2017 5:49 AM, Jon Chesterfield via llvm-dev wrote: > For example, truncating store of an i32 to i6. My assumption was that > this should write the low six bits of the i32 to somewhere in memory. > > Should the top 24 bits of a corresponding 32 bit region of memory be > unchanged, zero,  undefined? Unchanged. > Should the two bits that would round the i6 up to a byte
2018 May 09
1
What should a truncating store do?
On 09/15/2017 10:55 AM, Friedman, Eli via llvm-dev wrote: > On 9/15/2017 5:49 AM, Jon Chesterfield via llvm-dev wrote: >> For example, truncating store of an i32 to i6. My assumption was that this should write the low six bits of the i32 to somewhere in memory. >> >> Should the top 24 bits of a corresponding 32 bit region of memory be unchanged, zero, undefined? > >
2013 Apr 17
1
Merging big data.frame
Hi all, I am trying to merge 2 big data.frame. The problem is merge is memory intensive so R is going out of memory error: cannot allocate vector of size 360.1 Mb. To overcome this, I am exploring option of using data.table package. But its not helping in term of memory as merge in data.table is fast but not memory efficient. Similar error is coming. My inputs are inp1 V1 V2 1 a i1 2 a i2 3 a
2011 Sep 27
1
array extraction
hello everyone. Look at the following R idiom: a <- array(1:30,c(3,5,2)) M <- (matrix(1:15,c(3,5)) %% 4) < 2 a[M,] <- 0 Now, I think that "a[M,]" has an unambiguous meaning (to a human). However, the last line doesn't work as desired, but I expected it to...and it recently took me an indecent amount of time to debug an analogous case. Just to be explicit, I would
2009 Aug 20
2
Insert rows in between dataframes
Hi all, Can anyone suggest me how to insert rows in between data frames and also keep the ordering of row numbers correct? Estimate Std. Error t value Pr(>|t|) recmeanC2 9.275880e-17 6.322780e-17 1.467057e+00 0.14349903 recmeanC3 1.283534e-17 2.080644e-17 6.168929e-01 0.53781390
2015 Jul 24
0
[LLVMdev] SIMD for sdiv <2 x i64>
> On 24.07.2015, at 08:06, zhi chen <zchenhn at gmail.com> wrote: > > It seems that that it's hard to vectorize int64 in LLVM. For example, LLVM 3.4 generates very complicated code for the following IR. I am running on a Haswell processor. Is it because there is no alternative AVX/2 instructions for int64? The same thing also happens to zext <2 x i32> -> <2 x
2010 Aug 20
3
Has anyone used Sweave with the Beamer poster macro for Latex ?
Hello, I'm trying to make a poster in Latex using the beamer poster macro (http://www-i6.informatik.rwth-aachen.de/~dreuw/latexbeamerposter.php), and use Sweave to add in R output. This works fine for adding graphics and tables, but if I want to put code in, the file fails to build in Latex. My Rnw file looks like \documentclass[final,hyperref={pdfpagelabels=false}]{beamer}
2013 Apr 28
0
hierarchical confirmatory factor analysis with sem package
Hi, I am doing a hierarchical CFA using the sem package. I have 20 items, and I have 2 factors (F3 and F4), and also F1 and F2 are nested within F3. Here is the code that I have, but it is giving me an error message "Warning message: In eval(expr, envir, enclos) : Negative parameter variances. Model may be underidentified." and a further error "Error in summary.objectiveML(cfa,
2009 Aug 24
1
natural sorting a data frame /vector by row
How to NATURAL sort a vector or data frame* by row* , in ascending order ? V1 V2 V3 V4 i1 5.000000e-01 1.036197e-17 4.825338e+16 0.00000000 i10 4.001692e-18 1.365740e-17 2.930053e-01 0.76973827 i12 -1.052843e-17 1.324484e-17 -7.949081e-01 0.42735000 i13 2.571236e-17 1.357336e-17 1.894325e+00 0.05922715 i2
2017 Apr 01
6
[Bug 1140] New: nft dump invalid (flow table)
https://bugzilla.netfilter.org/show_bug.cgi?id=1140 Bug ID: 1140 Summary: nft dump invalid (flow table) Product: nftables Version: unspecified Hardware: x86_64 OS: other Status: NEW Severity: major Priority: P5 Component: nft Assignee: pablo at netfilter.org
2010 Jun 01
1
loop
Can any one help it will be very kind, loop statements I have this table and some more records, I want to reshape it V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 TP53 Dis1 Dis2 Dis3 Dis4 Dis5 Dis6 DCI New1 New2 New3 New4 FDI Hi2 H3 H4 GHD I1 I3 I4 I5 I6 I7 I8 I want my new table or matrix to be some thing like this V1 V2 V3 Tp53 Dis1 Dis2 Tp53 Dis1 Dis3 Tp53 Dis1 Dis4 Tp53 Dis1 Dis5 Tp53 Dis1 Dis6 Tp53 Dis2