search for: i64eqr64

Displaying 2 results from an estimated 2 matches for "i64eqr64".

2012 Jun 20
0
[LLVMdev] How to define macros in a tablegen file?
...'d think this'd already be in // a td file somewhere... :-) class CodeFrag<dag frag> { dag Fragment = frag; } class I64SETCCNegCond<PatFrag cond, CodeFrag compare>: Pat<(cond R64C:$rA, R64C:$rB), (XORIr32 compare.Fragment, -1)>; def : I64SETCCNegCond<setne, I64EQr64>; def : I64SELECTNegCond<setne, I64EQr64>; Sebastian -- Qualcomm Innovation Center, Inc is a member of Code Aurora Forum
2012 Jun 20
3
[LLVMdev] How to define macros in a tablegen file?
Hi Micah, On Tue, Jun 19, 2012 at 6:29 PM, Villmow, Micah <Micah.Villmow at amd.com> wrote: > If the patterns only include SDNodes, then pattern fragments will work. > > I might be wrong, but I've yet to find a way to do it with machine instructions, which is what you seem to have here. I found in the Cell SPU port: lib/Target/CellSPU/SPUMathInstr.td some examples using code