search for: i512

Hi, all I want to make a function such as void add512(uint512_t *pz, const uint512_t *px, const uint512_t *py) { *pz = *px + *py; } # uint512_t means 512-bit unsigned integer register. Then, I make a sample code: >cat t.ll define void @add512(i512*noalias %pz, i512*noalias %px, i512*noalias %py) { %x = load i512* %px %y = load i512* %py %z = add i512 %x, %y store i512 %z, i512* %pz ret void } >llc-3.6 -O3 -march=x86 t.ll -o - add512: pushl %ebp pushl %ebx pushl %edi pushl %esi su...

Hi everyone! Here, I have a question and am curious about i128. I want to know how the LLVM handle i128, because many compiler backend doesn't support i128 directly. So I am very curious and want to how the llvm handle this situation? Besides i128, such as i256, i512, even i24? Thanks. Best Regards Wu Zhao -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20150202/74395a81/attachment.html>

Hi, I am currently working on an opencl project based on LLVM, the target device is 32bit. I met a problem that some llvm passes like GVN SROA will generate some IR operating on wide integer types like i128 or i512. But the device does not support such kind of data type. Is there any idea on how to lower this kind of IR to only operate on i32 or vector of i32? Or is there any existing code handle this? Thanks! Ruiling -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://...

...appropriate for the architecture it is being compiled on)? In just a quick guess, I would say that something like an i4 would be compiled as if it was an i8, treated identically to an i8 in all circumstances, is this correct? Second, what if the specified integer size is rather large, say that an i512 was specified, would this cause a compile error (something along the lines of the specified integer size being too large to fit in the machine architecture), or would it rather compile in the necessary code to do bignum math on it (or would something like that be in the realm of the language design...

Hi LLVM, 1. Can mul and/or div support be added for big integer types like i256? 2. What are the limits? 3. If yes, how should it be done? I have experience only with X86 target and know that mul i128 works and div i128 is lowered to function call from compile-rt like library (what works only if you link with such library). Can that support be extended? - Paweł -------------- next part

...l.com> > wrote: > >> Hi, >> >> I am currently working on an opencl project based on LLVM, the target >> device is 32bit. >> I met a problem that some llvm passes like GVN SROA will generate some IR >> operating >> on wide integer types like i128 or i512. But the device does not support >> such kind of data type. >> Is there any idea on how to lower this kind of IR to only operate on i32 >> or vector of i32? Or is there any existing code handle this? >> >> Thanks! >> Ruiling >> >> ____________________...

...There is a whole pile of logic in lib/CodeGen/SelectionDAG/Legalize*Types.cpp in order to get this effect (currently you have to pass -enable-legalize-types to llc to turn on codegen support for funky integer sizes). > Second, what if the specified integer size is rather large, say that > an i512 was specified, would this cause a compile error (something > along the lines of the specified integer size being too large to fit > in the machine architecture), or would it rather compile in the > necessary code to do bignum math on it (or would something like that > be in the realm of...

Hi everyone. After lurking for a while, this is my first post to the list. I am working with some graduate students on the general topic of compiler support for SIMD programming and specific projects related to LLVM and my own Parabix technology (parabix.costar.sfu.ca). Right now we have a few course projects on the go and already a question arising out of one of them (SSE2 Hoisting).