Displaying 11 results from an estimated 11 matches for "i49".
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2013 Feb 09
1
Troubleshooting underidentification issues in structural equation modelling (SEM)
Hi all, hope someone can help me out with this.
Background Introduction
I have a data set consisting of data collected from a questionnaire that I
wish to validate. I have chosen to use confirmatory factor analysis to
analyse this data set.
Instrument
The instrument consists of 11 subscales. There is a total of 68 items in
the 11 subscales. Each item is scored on an integer scale between 1 to 4.
2010 May 23
0
Multimedia Fusion 2 Hardware Accleration is bugged
...en it again, then it returns to normal.
Next problem happens when I run application HWA (normal works well). Frame is normal size, but game is squeezed and scrolling is failing, because it scrolls like hot spot would be something else.
Screenshots:
Sometimes frame looks like this:
[Image: http://i49.tinypic.com/2u9pqm9.png ]
Game area is squeezed:
[Image: http://i48.tinypic.com/j80d9f.png ]
Background is set to 640x480, but when I test game it's squeezed:
[Image: http://i49.tinypic.com/6p5kcw.png ]
I report this as a bug and I ask, is there any way to make it working fine? o.o
2009 Dec 12
1
[LLVMdev] Adding multiples-of-8 integer types to MVT
...or which
bitwidth T <= 4 * bitwidth of LT
If there is one, take the smallest one (SLT) and promote T to 4*SLT.
Continue with 8*, 16* etc.
For example, if i24 and i32 are the legal types, with this algorithm
types i33, ..., i48 would be promoted to i48 then expanded to two lots
of i24. Types i49, ..., i64 would be promoted to i64 then expanded to
two lots of i32.
For example, if i10 and i32 are the legal types, i40 would be promoted
to i64 then expanded to two lots of i32.
Ciao,
Duncan.
2010 Sep 29
0
[LLVMdev] spilling & xmm register usage
....f32(float %tmp15.i33.i) nounwind
> %tmp17.i35.i = fmul float %call16.i34.i, 0x3FD9884540000000
> %tmp19.i37.i = fmul float %tmp17.i35.i, %tmp7.i25.i
> %tmp29.i47.i = fmul float %tmp7.i25.i, 0x3FF548CDE0000000
> %tmp30.i48.i = fadd float %tmp29.i47.i, 0xBFFD23DD40000000
> %tmp31.i49.i = fmul float %tmp7.i25.i, %tmp30.i48.i
> %tmp32.i50.i = fadd float %tmp31.i49.i, 0x3FFC80EF00000000
> %tmp33.i51.i = fmul float %tmp7.i25.i, %tmp32.i50.i
> %tmp34.i52.i = fadd float %tmp33.i51.i, 0xBFD6D1F0E0000000
> %tmp35.i53.i = fmul float %tmp7.i25.i, %tmp34.i52.i
> %tmp36...
2009 Dec 09
0
[LLVMdev] Adding multiples-of-8 integer types to MVT
On Saturday, December 05, 2009 7:34 AM, Duncan Sands wrote,
>
> >> Would there be any interest/opposition to extending the
> set of simple
> >> integer types in MVT to include the missing multiples of 8
> (up to 64
> >> bits)? That is: i24, i40, i48, i56?
>
> By the way, the integer type legalization logic should
> probably go like
> this: let
2010 Sep 29
3
[LLVMdev] spilling & xmm register usage
Hello everybody,
I have stumbled upon a test case (the attached module is a slightly
reduced version) that shows extremely reduced performance on linux
compared to windows when executed using LLVM's JIT.
We narrowed the problem down to the actual code being generated, the
source IR on both systems is the same.
Try compiling the attached module:
llc -O3 -filetype=asm -o BAD.s BAD.ll
Under
2009 Dec 05
2
[LLVMdev] Adding multiples-of-8 integer types to MVT
>> Would there be any interest/opposition to extending the set of simple
>> integer types in MVT to include the missing multiples of 8 (up to 64
>> bits)? That is: i24, i40, i48, i56?
By the way, the integer type legalization logic should probably go like
this: let T be an integer type.
(1) If T is legal, do nothing.
(2) If there is a legal integer type which is bigger (in
2013 Feb 14
1
[LLVMdev] LiveIntervals analysis problem
...[13 x i16]* %w.i to i8*
call void @llvm.lifetime.start(i64 -1, i8* %18) nounwind
%19 = load i32* %rndprc, align 4, !tbaa !3
br i1 %cmp.i.i, label %for.cond.preheader.i.i231, label %entry.if.end_crit_edge.i
entry.if.end_crit_edge.i: ; preds = %eisneg.exit
%incdec.ptr.i495.phi.trans.insert.i = getelementptr inbounds [13 x i16]* %e, i32 0, i32 1
%.pre996.i = load i16* %incdec.ptr.i495.phi.trans.insert.i, align 2, !tbaa !5
%incdec.ptr.1.i496.phi.trans.insert.i = getelementptr inbounds [13 x i16]* %e, i32 0, i32 2
%.pre997.i = load i16* %incdec.ptr.1.i496.phi.tra...
2017 Nov 13
2
Reaching definitions on Machine IR post register allocation
...38
>
> .
>
> .
>
> .
>
> CMP32mr %RDI, 4, %RSI, 1776, %noreg, %ECX, %EFLAGS<imp-def>;
> mem:LD4[%arrayidx.i49](tbaa=!2767) dbg:FastBoard.cpp:1947:26
>
> The relevant portion of the RDF graph that is constructed is shown below:
>
> BB#0:
>
> s3: MOV32r0 [d4<ECX>(,d50,u245):, d5<EFLAGS>!(,d7,):]
>
> .
>
> ...
2017 Nov 24
2
Reaching definitions on Machine IR post register allocation
....
>>>
>>> .
>>>
>>> .
>>>
>>> CMP32mr %RDI, 4, %RSI, 1776, %noreg, %ECX, %EFLAGS<imp-def>;
>>> mem:LD4[%arrayidx.i49](tbaa=!2767) dbg:FastBoard.cpp:1947:26
>>>
>>> The relevant portion of the RDF graph that is constructed is shown below:
>>>
>>> BB#0:
>>>
>>> s3: MOV32r0 [d4<ECX>(,d50,u245):, d5<EFLAGS>!(,d7,):]
>>>
>>>...
2017 Nov 01
2
Reaching definitions on Machine IR post register allocation
Hi Geoff/Krzyssztof,
Wouldn't the isRenamable() change be required even for the RDF based copy propagation? Maybe Hexagon does not impose ABI/ISA restrictions which require specific registers to be used in specific contexts.
Also, if Geoff's copy propagation pass is invoked post-RA wouldn't it need to handle the x86 ISA feature which allows 8 bit/16 bit values to be moved into a