search for: i32reg

Our architecture has 1-bit boolean predicate registers. I've defined comparison def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; But then I end up having the following bug: Code %0 = zext i8 %data to i32 %1 = zext i16 %crc to i32 %2 = xor i32 %1, %0 %3 = and i32 %2, 1 %4 = icmp eq i32 %3, 0 which compares the l...

On 29 Sep 2010, at 06:25, Heikki Kultala wrote: > Our architecture has 1-bit boolean predicate registers. > > I've defined comparison > > > def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; > > > > > But then I end up having the following bug: > > > Code > > > %0 = zext i8 %data to i32 > %1 = zext i16 %crc to i32 > %2 = xor i32 %1, %0 >...

...Sep 2010, at 06:25, Heikki Kultala wrote: >>>> >>>>> Our architecture has 1-bit boolean predicate registers. >>>>> >>>>> I've defined comparison >>>>> >>>>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; >>>>> >>>>> But then I end up having the following bug: >>>>> >>>>> Code >>>>> >>>>> %0 = zext i8 %data to i32...

...29 Sep 2010, at 06:25, Heikki Kultala wrote: >>>> >>>>> Our architecture has 1-bit boolean predicate registers. >>>>> >>>>> I've defined comparison >>>>> >>>>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; >>>>> >>>>> But then I end up having the following bug: >>>>> >>>>> Code >>>>> >>>>> %0 = zext i8 %data to i32 &g...

On Sep 29, 2010, at 12:36 AM, Heikki Kultala wrote: > On 29 Sep 2010, at 06:25, Heikki Kultala wrote: > >> Our architecture has 1-bit boolean predicate registers. >> >> I've defined comparison >> >> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; >> >> But then I end up having the following bug: >> >> Code >> >> %0 = zext i8 %data to i32 >> %1 = zext i16 %crc to i32 >> %2 = xor i32 %1, %0 >&gt...

...2:36 AM, Heikki Kultala wrote: > >> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >> >>> Our architecture has 1-bit boolean predicate registers. >>> >>> I've defined comparison >>> >>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; >>> >>> But then I end up having the following bug: >>> >>> Code >>> >>> %0 = zext i8 %data to i32 >>> %1 = zext i16 %crc to i32 >>&gt...

...> >>> On 29 Sep 2010, at 06:25, Heikki Kultala wrote: >>> >>>> Our architecture has 1-bit boolean predicate registers. >>>> >>>> I've defined comparison >>>> >>>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; >>>> >>>> But then I end up having the following bug: >>>> >>>> Code >>>> >>>> %0 = zext i8 %data to i32 >>>> %1 = z...

I tried to add a isel pattern [(set I32Regs:$dest, (select (seteq I32Regs:$op1, I32Regs:$op1), I32Regs:$op3, I32Regs:$op4))] for my instruction. I get an error message "Could not infer all types in a pattern!" Above the error message it prints error message line containing the name of my op and (set I32Regs:i32:$dest, (select:i...

...kki Kultala wrote: >>>>> >>>>>> Our architecture has 1-bit boolean predicate registers. >>>>>> >>>>>> I've defined comparison >>>>>> >>>>>> def NErrb : InstTCE<(outs I1Regs:$op3), (ins I32Regs:$op1,I32Regs:$op2), "", [(set I1Regs:$op3, (setne I32Regs:$op1, I32Regs:$op2))]>; >>>>>> >>>>>> But then I end up having the following bug: >>>>>> >>>>>> Code >>>>>> >>>>>> %...

...ng all the combinations out, I'd like to use nested foreach loops to generate, the problem I'm having is that I cannot seem to conditionally set a DAG node on the foreach variable. For example: foreach a in ["r", "I"] in { def ADD#a : Inst<!if(!eq(#a, "r"), i32Reg, i32imm)>; } So, is this possible? It seems to be no to me. What could be another way of doing this without having massive code duplication. Thanks, Micah -------------- next part -------------- An HTML attachment was scrubbed... URL: <http://lists.llvm.org/pipermail/llvm-dev/attachments/20...

...oblem I'm having is that I cannot seem to > > conditionally set a DAG node on the foreach variable. > > > > > > > > For example: > > > > foreach a in ["r", "I"] in { > > > > def ADD#a : Inst<!if(!eq(#a, "r"), i32Reg, i32imm)>; > > > > } > > > > > > > > So, is this possible? It seems to be no to me. What could be another > way of > > doing this without having massive code duplication. > > > > > > > > Thanks, > > > > Micah > &...

...combinations out, I’d like to use nested foreach > loops to generate, the problem I’m having is that I cannot seem to > conditionally set a DAG node on the foreach variable. > > > > For example: > > foreach a in [“r”, “I”] in { > > def ADD#a : Inst<!if(!eq(#a, “r”), i32Reg, i32imm)>; > > } > > > > So, is this possible? It seems to be no to me. What could be another way of > doing this without having massive code duplication. > > > > Thanks, > > Micah > > > _______________________________________________ > LLVM Dev...

...t seem to >> > conditionally set a DAG node on the foreach variable. >> > >> > >> > >> > For example: >> > >> > foreach a in ["r", "I"] in { >> > >> > def ADD#a : Inst<!if(!eq(#a, "r"), i32Reg, i32imm)>; >> > >> > } >> > >> > >> > >> > So, is this possible? It seems to be no to me. What could be another >> way of >> > doing this without having massive code duplication. >> > >> > >> > >&g...

Subject: type inference in nodes like setcc Versions: 2.6, 2.7 As for now, inputs of setcc node have to be same as its result, which is in contradiction to definition in TargetSelectionDAG.td. Example: i32reg <- (setgt i16, i16) Logically, this should be correct. However, tablegen considers it incorrect. Why? Note: I'm currently trying to rewrite tablegen to process this correctly.