Displaying 20 results from an estimated 31 matches for "i31".
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2020 Aug 14
6
Intel AMX programming model discussion.
...e remaining parameters are what AMX instructions require. This is the LLVM IR corresponding to the example code.
12 define dso_local void @api(i32 %cond, i16 signext %row, i16 signext %col) local_unnamed_addr #2 {
13 entry:
14 %tobool = icmp eq i32 %cond, 0
15 %sext = shl i16 %col, 8
16 %conv.i31 = ashr exact i16 %sext, 8
17 br i1 %tobool, label %if.else, label %if.then
18
19 if.then: ; preds = %entry
20 %0 = tail call <256 x i32> @llvm.x86.tileloadd64(i16 %row, i16 %conv.i31, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64...
2020 Aug 14
3
Intel AMX programming model discussion.
...e remaining parameters are what AMX instructions require. This is the LLVM IR corresponding to the example code.
12 define dso_local void @api(i32 %cond, i16 signext %row, i16 signext %col) local_unnamed_addr #2 {
13 entry:
14 %tobool = icmp eq i32 %cond, 0
15 %sext = shl i16 %col, 8
16 %conv.i31 = ashr exact i16 %sext, 8
17 br i1 %tobool, label %if.else, label %if.then
18
19 if.then: ; preds = %entry
20 %0 = tail call <256 x i32> @llvm.x86.tileloadd64(i16 %row, i16 %conv.i31, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64...
2020 Aug 18
2
Intel AMX programming model discussion.
...e remaining parameters are what AMX instructions require. This is the LLVM IR corresponding to the example code.
12 define dso_local void @api(i32 %cond, i16 signext %row, i16 signext %col) local_unnamed_addr #2 {
13 entry:
14 %tobool = icmp eq i32 %cond, 0
15 %sext = shl i16 %col, 8
16 %conv.i31 = ashr exact i16 %sext, 8
17 br i1 %tobool, label %if.else, label %if.then
18
19 if.then: ; preds = %entry
20 %0 = tail call <256 x i32> @llvm.x86.tileloadd64(i16 %row, i16 %conv.i31, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64...
2017 Sep 15
2
What should a truncating store do?
...111111. Or it can be written as a packed
vector which I think would resemble 0b00001111111111111111111111111111.
This would mean the memory layout changes depending on how/whether the
legaliser breaks large vectors down into smaller types. Is this the case?
For example, <4xi32> => <4 x i31> converts to two <2 x i32> => <2 x i31>
stores on a target with <2 x i32> legal but would not be split if <4 x i32>
were declared legal.
Thanks
Jon
On Fri, Sep 15, 2017 at 7:41 PM, Friedman, Eli <efriedma at codeaurora.org>
wrote:
> On 9/15/2017 11:30 AM,...
2020 Aug 19
2
Intel AMX programming model discussion.
...e remaining parameters are what AMX instructions require. This is the LLVM IR corresponding to the example code.
12 define dso_local void @api(i32 %cond, i16 signext %row, i16 signext %col) local_unnamed_addr #2 {
13 entry:
14 %tobool = icmp eq i32 %cond, 0
15 %sext = shl i16 %col, 8
16 %conv.i31 = ashr exact i16 %sext, 8
17 br i1 %tobool, label %if.else, label %if.then
18
19 if.then: ; preds = %entry
20 %0 = tail call <256 x i32> @llvm.x86.tileloadd64(i16 %row, i16 %conv.i31, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64...
2020 Aug 19
3
Intel AMX programming model discussion.
...e remaining parameters are what AMX instructions require. This is the LLVM IR corresponding to the example code.
12 define dso_local void @api(i32 %cond, i16 signext %row, i16 signext %col) local_unnamed_addr #2 {
13 entry:
14 %tobool = icmp eq i32 %cond, 0
15 %sext = shl i16 %col, 8
16 %conv.i31 = ashr exact i16 %sext, 8
17 br i1 %tobool, label %if.else, label %if.then
18
19 if.then: ; preds = %entry
20 %0 = tail call <256 x i32> @llvm.x86.tileloadd64(i16 %row, i16 %conv.i31, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64...
2009 Nov 29
5
[LLVMdev] JVM Backend
...ke
they're working on support for tail calls in the Da Vinci Machine[1].
> and break with run-time errors
When I said it raises an assertion, I meant at compile-time.
> on structs?
No, structs are supported. The only unsupported types at the moment
(as far as I am aware) are things like i31 and f80.
> I would love to be able to evaluate LLVM IR in a safe environment (like the
> JVM) for debugging purposes but this is too incomplete to be useful for me:
> my IR depends heavily upon tail calls and value types. Unfortunately, the
> MSIL backend and lli are also incomplete an...
2020 Aug 15
2
Intel AMX programming model discussion.
...e remaining parameters are what AMX instructions require. This is the LLVM IR corresponding to the example code.
12 define dso_local void @api(i32 %cond, i16 signext %row, i16 signext %col) local_unnamed_addr #2 {
13 entry:
14 %tobool = icmp eq i32 %cond, 0
15 %sext = shl i16 %col, 8
16 %conv.i31 = ashr exact i16 %sext, 8
17 br i1 %tobool, label %if.else, label %if.then
18
19 if.then: ; preds = %entry
20 %0 = tail call <256 x i32> @llvm.x86.tileloadd64(i16 %row, i16 %conv.i31, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64...
2020 Aug 19
2
Intel AMX programming model discussion.
...e remaining parameters are what AMX instructions require. This is the LLVM IR corresponding to the example code.
12 define dso_local void @api(i32 %cond, i16 signext %row, i16 signext %col) local_unnamed_addr #2 {
13 entry:
14 %tobool = icmp eq i32 %cond, 0
15 %sext = shl i16 %col, 8
16 %conv.i31 = ashr exact i16 %sext, 8
17 br i1 %tobool, label %if.else, label %if.then
18
19 if.then: ; preds = %entry
20 %0 = tail call <256 x i32> @llvm.x86.tileloadd64(i16 %row, i16 %conv.i31, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64...
2020 Aug 14
2
Intel AMX programming model discussion.
...e remaining parameters are what AMX instructions require. This is the LLVM IR corresponding to the example code.
12 define dso_local void @api(i32 %cond, i16 signext %row, i16 signext %col) local_unnamed_addr #2 {
13 entry:
14 %tobool = icmp eq i32 %cond, 0
15 %sext = shl i16 %col, 8
16 %conv.i31 = ashr exact i16 %sext, 8
17 br i1 %tobool, label %if.else, label %if.then
18
19 if.then: ; preds = %entry
20 %0 = tail call <256 x i32> @llvm.x86.tileloadd64(i16 %row, i16 %conv.i31, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64...
2005 Aug 09
1
cannot boot any domU - case #2
...;APIC IRQ transform: (B0,I29,P0) -> 16
(XEN) PCI->APIC IRQ transform: (B0,I29,P1) -> 19
(XEN) PCI->APIC IRQ transform: (B0,I29,P2) -> 18
(XEN) PCI->APIC IRQ transform: (B0,I29,P0) -> 16
(XEN) PCI->APIC IRQ transform: (B0,I29,P3) -> 23
(XEN) PCI->APIC IRQ transform: (B0,I31,P0) -> 18
(XEN) PCI->APIC IRQ transform: (B0,I31,P0) -> 18
(XEN) PCI->APIC IRQ transform: (B0,I31,P1) -> 17
(XEN) PCI->APIC IRQ transform: (B0,I31,P1) -> 17
(XEN) PCI->APIC IRQ transform: (B1,I0,P0) -> 16
(XEN) PCI->APIC IRQ transform: (B2,I1,P0) -> 17
(XEN) PCI->...
2020 Aug 19
3
Intel AMX programming model discussion.
...e remaining parameters are what AMX instructions require. This is the LLVM IR corresponding to the example code.
12 define dso_local void @api(i32 %cond, i16 signext %row, i16 signext %col) local_unnamed_addr #2 {
13 entry:
14 %tobool = icmp eq i32 %cond, 0
15 %sext = shl i16 %col, 8
16 %conv.i31 = ashr exact i16 %sext, 8
17 br i1 %tobool, label %if.else, label %if.then
18
19 if.then: ; preds = %entry
20 %0 = tail call <256 x i32> @llvm.x86.tileloadd64(i16 %row, i16 %conv.i31, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64...
2009 Nov 29
0
[LLVMdev] JVM Backend
...xcellent TCO implementation
in LLVM.
> > and break with run-time errors
>
> When I said it raises an assertion, I meant at compile-time.
>
> > on structs?
>
> No, structs are supported. The only unsupported types at the moment
> (as far as I am aware) are things like i31 and f80.
How do you support structs when the JVM is incapable of expressing value
types? Do you box every aggregate in an object? Does insertvalue construct an
entirely new object? If so, the performance degradation will be orders of
magnitude. Optimizing structs for the JVM is not easy and you...
2020 Aug 20
1
Intel AMX programming model discussion.
...col)
> local_unnamed_addr #2 {
>
> 13 entry:
>
> 14 %tobool = icmp eq i32 %cond, 0
>
> 15 %sext = shl i16 %col, 8
>
> 16 %conv.i31 = ashr exact i16 %sext, 8
>
> 17 br i1 %tobool, label %if.else, label
> %if.then
>
> 18
>
> 19 if.then: ; preds = %entry
>
> 20 ...
2009 Nov 25
0
[LLVMdev] JVM Backend
...in the backend
dir, etc? It will be nice if this library be somehow integrated into
LLVM as well.
The current big question is: how you're planning to deal with
arbitrary precision stuff which might come from LLVM IR. Currently all
the things seems to behave different in case of receiving e.g. i31:
- functions like getTypeName() return some junk (the case
Type::IntegerTypeID just falls through to Type::FloatTyID)
- other functions just assert
--
With best regards, Anton Korobeynikov
Faculty of Mathematics and Mechanics, Saint Petersburg State University
2018 Jun 29
2
Cleaning up ‘br i1 false’ cases in CodeGenPrepare
....i
%call.i = tail call i32 @check_func() #5
br label %cond.false.i29
if.end.thread53: ; preds = %if.then
%2 = bitcast [16 x i8]* %source18 to i8*
%call10.i = call i8* @copy2(i64 16, i8* nonnull %2, i8* nonnull %py_src, i64 %conv) #5
br label %cond.false9.i31
if.end: ; preds = %entry
br i1 false, label %cond.true5.i26, label %cond.false9.i31
cond.true5.i26: ; preds = %if.end
%3 = trunc i64 %conv to i32
%cmp6.i25 = icmp ugt i32 %3, 16
br i1 %cmp6.i25, label %cond.fals...
2013 Feb 09
1
Troubleshooting underidentification issues in structural equation modelling (SEM)
Hi all, hope someone can help me out with this.
Background Introduction
I have a data set consisting of data collected from a questionnaire that I
wish to validate. I have chosen to use confirmatory factor analysis to
analyse this data set.
Instrument
The instrument consists of 11 subscales. There is a total of 68 items in
the 11 subscales. Each item is scored on an integer scale between 1 to 4.
2020 Aug 21
2
Intel AMX programming model discussion.
...e remaining parameters are what AMX instructions require. This is the LLVM IR corresponding to the example code.
12 define dso_local void @api(i32 %cond, i16 signext %row, i16 signext %col) local_unnamed_addr #2 {
13 entry:
14 %tobool = icmp eq i32 %cond, 0
15 %sext = shl i16 %col, 8
16 %conv.i31 = ashr exact i16 %sext, 8
17 br i1 %tobool, label %if.else, label %if.then
18
19 if.then: ; preds = %entry
20 %0 = tail call <256 x i32> @llvm.x86.tileloadd64(i16 %row, i16 %conv.i31, i8* getelementptr inbounds ([1024 x i8], [1024 x i8]* @buf, i64...
2009 Nov 29
0
[LLVMdev] JVM Backend
Hi David,
> No, structs are supported. The only unsupported types at the moment
> (as far as I am aware) are things like i31 and f80.
for funky sized integers, the most important operations to support are
loads and stores, shifts and logical operations (and, or, xor). These
are the ones that the optimizers like to introduce most. The logical
operations are straightforward. Loads and stores of iN are equivalent
to usi...
2009 Nov 24
2
[LLVMdev] JVM Backend
Hi,
I've written a backend for LLVM that allows LLVM IR to be transformed
to a Java/JVM class file (llvm-jvm.patch.gz attached).
Indirect function calls don't work yet, and there's probably some
minor bugs in it, but it works well for the test cases that I've run
through it. Also, several instructions are emulated by method calls
due to deficiencies in the JVM instruction set