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f256mem
2017 Dec 11
2
New x86 instruction with opcode 0x0F 0x7A
Hi all,
I'm trying to simulate an extended x86 architecture on gem5 with several
new instructions. My hardware setup is done and now I'd like llvm to accept
the existence of the new instruction passed in inline assembly and output
the correct opcode and registers. I chose the two-byte opcode 0x0F 0x7A and
I would like the instruction to have the same operands and return values
as CVTPS2PI