search for: i1's

...sregard prior knowledge of how this is handled by instcombine or how this is lowered by your favorite target...of course we'll fix it. :) Some answers in the links below if you do want to know. Which, if any, of these is canonical? 1. Is a zext simpler than a select? a. define i32 @sel_1_or_0(i1 %a) { %b = select i1 %a, i32 1, i32 0 ret i32 %b } b. define i32 @sel_1_or_0(i1 %a) { %b = zext i1 %a to i32 ret i32 %b } 2. What if we have to 'not' the bool? a. define i32 @sel_0_or_1(i1 %a) { %b = select i1 %a, i32 0, i32 1 ret i32 %b } b. define i32 @sel_0_or_1(i1 %a) {...

...front end for an existing interpreted language with slightly odd semantics for primitive values. Similar to the values in a database table, any value could be null, even for non-pointer types. For example a boolean variable could be true, false, or null. To model this behaviour, I'm passing an {i1, [type]} around for every numeric type. And using insertvalue / extractvalue all over the place. So when compiling this simple CS example; function long fib (long al_x) long ll_i=0, ll_ret=0, ll_last=0, ll_last2=1 if isnull(al_x) then return al_x end if ll_i=1 do while ll_i<=al_x ll_...

...uot; has missed some opportunities for optimization: define void @spa.main() readonly { entry: %tmp = load i32* @dst-ip ; <i32> [#uses=3] %tmp1 = and i32 %tmp, -16777216 ; <i32> [#uses=1] %tmp2 = icmp eq i32 %tmp1, 167772160 ; <i1> [#uses=2] %tmp3 = and i32 %tmp, -65536 ; <i32> [#uses=2] %tmp4 = icmp ne i32 %tmp3, 168296448 ; <i1> [#uses=1] %tmp5 = and i1 %tmp2, %tmp4 ; <i1> [#uses=1] %tmp6 = and i32 %tmp, -256 ; <i32> [...

I'm seeing some behavior that surprised me in writing an <8 x i1> vector to memory and reading it back. (Specifically, the surprise is that I didn't get the original value back!). This happens both with TOT and 2.9. This program illustrates the issue: define i32 @foo() { %c = alloca <8 x i1> store <8 x i1> <i1 true, i1 false, i1 fal...

...ffect on bzip2: 36 branches are completely removed, 1 is changed from conditional to unconditional, various bits of dead code are eliminated (not a lot, 4 stores and a few computations). I chose this example randomly, but it's typical of what I see elsewhere. Ciao, Duncan. > > define i1 @t1(i1 %c) { > br i1 %c, label %t, label %f > t: > ret i1 %c > f: > ret i1 %c > } > should be > br i1 R0, label %t, label %f > t: > ret R0 > f: > ret R0 > > However, with your pass > define i1 @t1(i1 %c) { > br i1 %c,...

...void @fn_0000000000000000(i8*, i8*, i8*) { bb: %res = alloca i32 %3 = load i32* %res %4 = bitcast i8* %0 to i32* %5 = load i32* %4 %6 = bitcast i8* %0 to i32* %7 = load i32* %6 %8 = xor i32 %5, %7 store volatile i32 %8, i32* %res %9 = load i32* %res %10 = icmp eq i32 %9, 0 br i1 %10, label %then, label %else merged: ; preds = %else, %then %11 = load i32* %res %12 = and i32 %11, -2147483648 %13 = icmp eq i32 %12, 0 br i1 %13, label %then3, label %else4 then: ; preds = %bb %zf =...

Hi All, AVX-512 introduced the K mask registers and masked operations which make a natural choice for legalizing vectors of i1's. For example, define <8 x i32> @foo(<8 x i32>%a, <8 x i32*> %p) { %r = call <8 x i32> @llvm.masked.gather.v8i32(<8 x i32*> %p, i32 4, <8 x i1> <i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true, i1 true>, <8 x i32> undef) re...

Then I misunderstood it's purpose. I see now that constant propagation could remove branches because you know a value is true. I was looking at the problem through my 'register allocator' lens. Here is a more expressive example of what you are doing. define i1 @t1(i1 %c) { br i1 %c, label %t, label %f t: br i1 %c, label %t2, label %f2 t2: code... ret something f2: code... ret something f: br i1 %c, label %t3, label %f3 t3: code... ret something f3: code... ret something } Would be changed into: define i1 @t1(i1 %c) { br i1...

...mp.1 = alloca i32 > %tmp.i = insertelement <2 x i32*> undef, i32* %tmp.0, i32 0 > %tmp = insertelement <2 x i32*> %tmp.i, i32* %tmp.1, i32 1 > ; Read from in1 and in2 > %in1.v = call <2 x i32> @llvm.masked.gather.v2i32(<2 x i32*> %in1, i32 > 1, <2 x i1> <i1 true, i1 true>, <2 x i32> undef) #1 > %in2.v = call <2 x i32> @llvm.masked.gather.v2i32(<2 x i32*> %in2, i32 > 1, <2 x i1> <i1 true, i1 true>, <2 x i32> undef) #1 > ; Store in1 to the allocas > call void @llvm.masked.scatter.v2i32(...

...en.bc' source_filename = "/tmp/autogen.bc" define void @autogen_SD29355(i8*, i32*, i64*, i32, i64, i8) { BB: %A4 = alloca double %A3 = alloca float %A2 = alloca i8 %A1 = alloca double %A = alloca i64 %L = load i8, i8* %0 store i8 33, i8* %0 %E = extractelement <8 x i1> zeroinitializer, i32 2 br label %CF261 CF261: ; preds = %BB %Shuff = shufflevector <2 x i16> zeroinitializer, <2 x i16> zeroinitializer, <2 x i32> <i32 undef, i32 3> %I = insertelement <8 x i8> zeroinitializer, i8 6...

I've been debugging some strange happenings over here and I put an assert in APInt to catch what I think is the source of the problem: int64_t getSExtValue() const { // An i1 -1 is unrepresentable. assert(BitWidth != 1 && "Signed i1 value is not representable!"); To me an i1 -1 makes no sense whatsoever. It is not representable in twos-complement form. It cannot be distinguished from unsigned i1 1. It turns out this assert triggers all over the...

> Transforms/InstCombine/select.ll > ================================ > define i1 @trueval_is_true(i1 %C, i1 %X) { >  %R = select i1 %C, i1 1, i1 %X >  ret i1 %R > } > => > define i1 @trueval_is_true(i1 %C, i1 %X) { >  %R = or i1 %C, %X >  ret i1 %R > } > ERROR: Target is more poisonous than source (when %C = #x1 & %X = poison) > > (t...

Are you sure this is really advantageous? '%c' is only one variable, but when you add the constant propagation, '%c' and false/true are two different variables. Thus define i1 @t1(i1 %c) { br i1 %c, label %t, label %f t: ret i1 %c f: ret i1 %c } should be br i1 R0, label %t, label %f t: ret R0 f: ret R0 However, with your pass define i1 @t1(i1 %c) { br i1 %c, label %t, label %f t: ret i1 true f: ret i1 false } will be define i1 @t1(i1 %c)...

I converted now my back-end with legal i1 lowering to the 2.6 branch and my original problem with the DAG combiner didn't occur any more and seems to be fixed. setOperationAction(ISD::OR, MVT::i1, Promote) also works fine for logical operations. > What is your SetCCResultType now? I changed SetCCResultType to return MVT::i1 type....

Hi friends, Please can anyone help me with an easier solution of doing the below mentioned work. Suppose i have a dataset like this:--- i1 i2 i3 i4 i5 1 7 13 1 2 2 8 14 2 2 3 9 15 3 3 4 10 16 4 4 5 11 17 5 5 6 12 18 6 7 *i1,i2,i3,i4,i5 are my items.I am able to find all possible pairs i.e Say this dataframe is "item_pairs" **i1,i2 **i1,i3 **i1,i4 i1,i5 **i2,i1 **i2,i3 i2,i4 i2,i5 **i3,i1 **i3,i2 **i...

On Tue, Sep 6, 2011 at 4:37 PM, Matt Pharr <matt.pharr at gmail.com> wrote: > I'm seeing some behavior that surprised me in writing an <8 x i1> vector to memory and reading it back.  (Specifically, the surprise is that I didn't get the original value back!).  This happens both with TOT and 2.9.  This program illustrates the issue: > > define i32 @foo() { >  %c = alloca <8 x i1> >  store <8 x i1> <i1 true,...

...a conditional branch instruction then it replaces all occurrences of the condition in the true block with "true" and in the false block with "false". Well, OK, it is a bit more sophisticated (and a bit more careful!) than that but you get the idea. It will turn this define i1 @t1(i1 %c) { br i1 %c, label %t, label %f t: ret i1 %c f: ret i1 %c } into this define i1 @t1(i1 %c) { br i1 %c, label %t, label %f t: ret i1 true f: ret i1 false } for example. Curiously enough LLVM doesn't seem to have a pass that does this....

...nxxxxx1, I hear the demo-thanks file, and then it dials out. My cellphone rings, but as soon as I pick up the call, the calls hangs up : -- Accepting call from '418nxxxxx2' to '418nxxxxx1' on channel 0/1, span 1 -- Executing [418nxxxxx1 at ael-default:1] Answer("DAHDI/i1/418nxxxxx2-b", "") in new stack -- Executing [418nxxxxx1 at ael-default:2] Wait("DAHDI/i1/418nxxxxx2-b", "2") in new stack -- Executing [418nxxxxx1 at ael-default:3] Playback("DAHDI/i1/418nxxxxx2-b", "demo-thanks") in new stack -...

Hello, Context: We have a backend where v32i1 is a Legal type, but the storage for v32i1 is not 32-bits/uses a different instruction sequence. We ran into an issue because combineLoadToOperationType changed v32i1 loads into i32 loads, so a sequence like: define void @bits(<32 x i1>* %A, <32 x i1>* %B) { %a = load <32 x i1>,...

...sertelement <2 x i32*> undef, i32* %tmp.0, i32 0 > >> %tmp = insertelement <2 x i32*> %tmp.i, i32* %tmp.1, i32 1 > >> ; Read from in1 and in2 > >> %in1.v = call <2 x i32> @llvm.masked.gather.v2i32(<2 x i32*> %in1, i32 > >> 1, <2 x i1> <i1 true, i1 true>, <2 x i32> undef) #1 > >> %in2.v = call <2 x i32> @llvm.masked.gather.v2i32(<2 x i32*> %in2, i32 > >> 1, <2 x i1> <i1 true, i1 true>, <2 x i32> undef) #1 > >> ; Store in1 to the allocas > >> c...