search for: hwport1

Hi, I’m trying to work out the behavior of llvm-mca on instructions with ProcResGroups. My current understanding is: When an instruction requests a port group (e.g., HWPort015) and all of its atomic sub-resources (e.g., HWPort0,HWPort1,HWPort5), HWPort015 is marked as “reserved” and is issued in parallel with HWPort0, HWPort1, and HWPort5, blocking future instructions from reserving HWPort015 for the duration but not explicitly blocking any of HWPort0, HWPort1, or HWPort5 (although those ports are in fact blocked because the inst...

...e to not crash when resource > groups overlap without all atomic subunits being specified: > > `echo 'fxrstor (%rsp)' | llvm-mca -mtriple=x86_64-unknown-unknown > -march=x86-64 -mcpu=haswell` > crashes (because fxrstor requests > `HWPort0,HWPort6,HWPort23,HWPort05,HWPort06,HWPort15,HWPort0156`, so > HWPort0156 ends up asserting because 0,1,5, and 6 are all taken), so I > added: > ``` > --- a/llvm/lib/MCA/HardwareUnits/ResourceManager.cpp > +++ b/llvm/lib/MCA/HardwareUnits/ResourceManager.cpp > @@ -292,7 +292,7 @@ void ResourceManager::issueInstruction( >...

...o declare which pipeline resources are consumed, and for how long (in number cycles). So we cannot accurately describe to mca that the delayed consumption of the ALU pipe. > Now think about what happens if: the first shuffle uOP consumes 1cy of HWPort0, and the second shuffle uOp consumes 1cy of HWPort1, and the ADD consumes 1cy of HWPort01. We end up in that "odd" situation you described where HWPort01 is "reserved" for 1cy. > In reality, that 1cy of HWPort01 should have started 1cy after the other two opcodes. At that point, both pipelines would have been seen available. &...

We have a two different dimensions for each instruction: slot assignments, and operand timings. These two are unrelated to each other, and also each (or both) can change for any given instruction from one architecture version to the next. The main concern for us was which of these mechanisms contains all the information that we need. We cannot express all the scheduling details by hand, and

Hi Krzysztof, 2018-02-08 13:32 GMT+08:00 Andrew Trick via llvm-dev < llvm-dev at lists.llvm.org>: > > > On Feb 4, 2018, at 9:15 AM, Yatsina, Marina via llvm-dev < > llvm-dev at lists.llvm.org> wrote: > > Hi, > > What is the best way to model a scheduler for a VLIW in-order architecture? > I’ve looked at the Hexagon and R600 architectures and they are using