search for: hw_ver

...+ clk_disable_unprepare(slim_rproc->clks[clk]); + + return ret; +} + +/** + * Remoteproc slim specific device handlers + */ +static int slim_rproc_start(struct rproc *rproc) +{ + struct device *dev = &rproc->dev; + struct st_slim_rproc *slim_rproc = rproc->priv; + unsigned long hw_id, hw_ver, fw_rev; + u32 val; + int ret; + + ret = slim_clk_enable(slim_rproc); + if (ret) { + dev_err(dev, "Failed to enable clocks\n"); + return ret; + } + + /* disable CPU pipeline clock & reset cpu pipeline */ + val = SLIM_CLK_GATE_DIS | SLIM_CLK_GATE_RESET; + writel(val, slim_rproc->s...

...m specific device handlers > + */ I suggest not using kernel-doc format for this type of comment. > +static int slim_rproc_start(struct rproc *rproc) > +{ > + struct device *dev = &rproc->dev; > + struct st_slim_rproc *slim_rproc = rproc->priv; > + unsigned long hw_id, hw_ver, fw_rev; > + u32 val; > + int ret; > + > + ret = slim_clk_enable(slim_rproc); > + if (ret) { > + dev_err(dev, "Failed to enable clocks\n"); > + return ret; > + } > + > + /* disable CPU pipeline clock & reset cpu pipeline */ Be consistent. Is it 'c...

...m specific device handlers > + */ I suggest not using kernel-doc format for this type of comment. > +static int slim_rproc_start(struct rproc *rproc) > +{ > + struct device *dev = &rproc->dev; > + struct st_slim_rproc *slim_rproc = rproc->priv; > + unsigned long hw_id, hw_ver, fw_rev; > + u32 val; > + int ret; > + > + ret = slim_clk_enable(slim_rproc); > + if (ret) { > + dev_err(dev, "Failed to enable clocks\n"); > + return ret; > + } > + > + /* disable CPU pipeline clock & reset cpu pipeline */ Be consistent. Is it 'c...

...ggest not using kernel-doc format for this type of comment. Will fix. > > > +static int slim_rproc_start(struct rproc *rproc) > > +{ > > + struct device *dev = &rproc->dev; > > + struct st_slim_rproc *slim_rproc = rproc->priv; > > + unsigned long hw_id, hw_ver, fw_rev; > > + u32 val; > > + int ret; > > + > > + ret = slim_clk_enable(slim_rproc); > > + if (ret) { > > + dev_err(dev, "Failed to enable clocks\n"); > > + return ret; > > + } > > + > > + /* disable CPU pipeline clock & r...

Hi have what might be some elementary questions. Really, what I"d love would be for someone who has had good success to publish his/her configuration files and, maybe, the output from ifconfig. At this point, when I see the not-so-good performance I"m getting, I don't realistically know if I'm in the right ballfield. It seems to me, that with so many mellanox cards out

...InfiniBand (0) fw_ver: 2.9.1000 node_guid: 0002:c903:000c:1e82 sys_image_guid: 0002:c903:000c:1e85 vendor_id: 0x02c9 vendor_part_id: 26428 hw_ver: 0xB0 board_id: IBM0D90000009 phys_port_cnt: 1 port: 1 state: PORT_ACTIVE (4) max_mtu: 4096 (5) ac...

This issue was brought up about a year and a half ago. So I''ll bring it up again and see if anything happens. I''ve got an infiniband network and am attempting to pass the infiniband card through the host and give it to the guest. I''m working with standard CentOS 5.2 on both guest and host with their provided xen (3.0.3 ish). I''ve also attempted to install the

This issue was brought up about a year and a half ago. So I''ll bring it up again and see if anything happens. I''ve got an infiniband network and am attempting to pass the infiniband card through the host and give it to the guest. I''m working with standard CentOS 5.2 on both guest and host with their provided xen (3.0.3 ish). I''ve also attempted to install the

Hi Vinod, Bjorn, Patrice, This patchset adds support for the Flexible Direct Memory Access (FDMA) core found on STi chipsets from STMicroelectronics. The FDMA is a slim core CPU with a dedicated firmware. It is a general purpose DMA controller supporting 16 independent channels and data can be moved from memory to memory or between memory and paced latency critical real time targets. After quite

Hi Vinod, Bjorn, Patrice, This patchset adds support for the Flexible Direct Memory Access (FDMA) core found on STi chipsets from STMicroelectronics. The FDMA is a slim core CPU with a dedicated firmware. It is a general purpose DMA controller supporting 16 independent channels and data can be moved from memory to memory or between memory and paced latency critical real time targets. After quite

...+ int offs; + size_t s; + + addrconf_addr_eui48((unsigned char *)&attr.sys_image_guid, + (const char *)&rdev->netdev->mac); + + attr.max_mr_size = 4096; + attr.page_size_cap = 4096; + attr.vendor_id = 1; + attr.vendor_part_id = 1; + attr.hw_ver = VIRTIO_RDMA_HW_VER; + attr.max_qp = 1024; + attr.max_qp_wr = 1024; + attr.device_cap_flags = 0; + attr.max_sge = 64; + attr.max_sge_rd = 64; + attr.max_cq = 1024; + attr.max_cqe = 64; + attr.max_mr = 1024; + attr.max_pd = 1024; + attr.max_qp_rd_atom = 0; + attr.ma...

Data center backends use more and more RDMA or RoCE devices and more and more software runs in virtualized environment. There is a need for a standard to enable RDMA/RoCE on Virtual Machines. Virtio is the optimal solution since is the de-facto para-virtualizaton technology and also because the Virtio specification allows Hardware Vendors to support Virtio protocol natively in order to achieve

Data center backends use more and more RDMA or RoCE devices and more and more software runs in virtualized environment. There is a need for a standard to enable RDMA/RoCE on Virtual Machines. Virtio is the optimal solution since is the de-facto para-virtualizaton technology and also because the Virtio specification allows Hardware Vendors to support Virtio protocol natively in order to achieve