search for: hvm_vmx

...) + vmx_set_eoi_exit_bitmap(v, pt_vector); + + /* we need update the RVI field */ + status &= ~(unsigned long)0x0FF; + status |= (unsigned long)0x0FF & + intack.vector; + __vmwrite(GUEST_INTR_STATUS, status); + if (v->arch.hvm_vmx.eoi_exitmap_changed) { +#ifdef __i386__ +#define UPDATE_EOI_EXITMAP(v, e) { \ + if (test_and_clear_bit(e, &v->arch.hvm_vmx.eoi_exitmap_changed)) { \ + __vmwrite(EOI_EXIT_BITMAP##e, v->arch.hvm_vmx.eoi_exit_bitmap[e]); \ +...

Changes from v2 to v3: - Use pfn_to_paddr() to get the address from frame number instead of doing shift directly. - Remove some unnecessary initialization code and add "static" to vmentry_fields and gpdptr_fields. - Enable the VMREAD/VMWRITE bitmap only if nested hvm is enabled. - Use clear_page() to set all 0 to the page instead of memset(). - Use domheap to allocate the

...EAD/VMWRITE bitmap. */ @@ -75,7 +75,7 @@ int nvmx_vcpu_initialise(struct vcpu *v) if ( !vmread_bitmap ) { gdprintk(XENLOG_ERR, "nest: allocation for vmread bitmap failed\n"); - goto out1; + return -ENOMEM; } v->arch.hvm_vmx.vmread_bitmap = vmread_bitmap; @@ -83,7 +83,7 @@ int nvmx_vcpu_initialise(struct vcpu *v) if ( !vmwrite_bitmap ) { gdprintk(XENLOG_ERR, "nest: allocation for vmwrite bitmap failed\n"); - goto out2; + return -ENOMEM; }...

...YPE_W) - __clear_bit(msr, msr_bitmap + 0xc00/BYTES_PER_LONG); /* write-high */ + clear_bit(msr, msr_bitmap + 0xc00/BYTES_PER_LONG); /* write-high */ + } +} + +void vmx_enable_intercept_for_msr(struct vcpu *v, u32 msr, int type) +{ + unsigned long *msr_bitmap = v->arch.hvm_vmx.msr_bitmap; + + /* VMX MSR bitmap supported? */ + if ( msr_bitmap == NULL ) + return; + + /* + * See Intel PRM Vol. 3, 20.6.9 (MSR-Bitmap Address). Early manuals + * have the write-low and read-high bitmap offsets the wrong way round. + * We can control MSRs 0x00000000-0...

...t;eip = __vmread(GUEST_RIP); + +#ifdef HVM_DEBUG_SUSPEND + printk("vmx_vmcs_save: inst_len=0x%lx, eip=0x%"PRIx64".\n", + inst_len, c->eip); +#endif + + c->esp = __vmread(GUEST_RSP); + c->eflags = __vmread(GUEST_RFLAGS); + + c->cr0 = v->arch.hvm_vmx.cpu_shadow_cr0; + c->cr3 = v->arch.hvm_vmx.cpu_cr3; + c->cr4 = v->arch.hvm_vmx.cpu_shadow_cr4; + +#ifdef HVM_DEBUG_SUSPEND + printk("vmx_vmcs_save: cr3=0x%"PRIx64", cr0=0x%"PRIx64", cr4=0x%"PRIx64".\n", + c->cr3, +...

From: Yang Zhang <yang.z.zhang@Intel.com> The follwoing patches are adding the Posted Interrupt supporting to Xen: Posted Interrupt allows vAPIC interrupts to inject into guest directly without any vmexit. - When delivering a interrupt to guest, if target vcpu is running, update Posted-interrupt requests bitmap and send a notification event to the vcpu. Then the vcpu will handle this

...c b/xen/arch/x86/hvm/vmx/vvmx.c index 2e0b79d..1f610eb 100644 --- a/xen/arch/x86/hvm/vmx/vvmx.c +++ b/xen/arch/x86/hvm/vmx/vvmx.c @@ -57,6 +57,9 @@ void nvmx_vcpu_destroy(struct vcpu *v) { struct nestedvcpu *nvcpu = &vcpu_nestedhvm(v); + if ( nvcpu->nv_n1vmcx ) + v->arch.hvm_vmx.vmcs = nvcpu->nv_n1vmcx; + nvmx_purge_vvmcs(v); if ( nvcpu->nv_n2vmcx ) { __vmpclear(virt_to_maddr(nvcpu->nv_n2vmcx)); @@ -65,6 +68,14 @@ void nvmx_vcpu_destroy(struct vcpu *v) } } +void nvmx_domain_relinquish_resources(struct domain *d) +{ + struct vcpu *v;...

...vmwrite(VM_ENTRY_CONTROLS, vmx_vmentry_control); + if ( cpu_has_vmx_ple ) + { + __vmwrite(PLE_GAP, ple_gap); + __vmwrite(PLE_WINDOW, ple_window); + } + if ( cpu_has_vmx_secondary_exec_control ) __vmwrite(SECONDARY_VM_EXEC_CONTROL, v->arch.hvm_vmx.secondary_exec_control); Index: hv/xen/arch/x86/hvm/vmx/vmx.c =================================================================== --- hv.orig/xen/arch/x86/hvm/vmx/vmx.c +++ hv/xen/arch/x86/hvm/vmx/vmx.c @@ -2617,6 +2617,13 @@ asmlinkage void vmx_vmexit_handler(struc break; } + ca...

...ng Hao <xudong.hao@intel.com> diff -r cd4dd23a831d xen/arch/x86/hvm/vmx/vmx.c --- a/xen/arch/x86/hvm/vmx/vmx.c Fri May 11 18:59:07 2012 +0100 +++ b/xen/arch/x86/hvm/vmx/vmx.c Wed May 15 02:31:34 2013 +0800 @@ -1350,6 +1350,19 @@ static void __vmx_inject_exception(int t curr->arch.hvm_vmx.vmx_emulate = 1; } +/* + * Generate the virtual event to guest. + * NOTE: + * This is for processor execution generated exceptions, + * and INT 3(CC), INTO (CE) instruction emulation. It is + * not intended for the delivery of event due to emulation + * of INT nn (CD nn) instruction, which...

...us |= (unsigned long)0x0FF & + status &= ~(unsigned long)VMX_GUEST_INTR_STATUS_SUBFIELD_BITMASK; + status |= (unsigned long)VMX_GUEST_INTR_STATUS_SUBFIELD_BITMASK & intack.vector; __vmwrite(GUEST_INTR_STATUS, status); if (v->arch.hvm_vmx.eoi_exitmap_changed) { diff --git a/xen/arch/x86/hvm/vmx/vmx.c b/xen/arch/x86/hvm/vmx/vmx.c index 4d7c93f..43ed36c 100644 --- a/xen/arch/x86/hvm/vmx/vmx.c +++ b/xen/arch/x86/hvm/vmx/vmx.c @@ -1419,6 +1419,28 @@ static int vmx_virtual_intr_delivery_enabled(void) return cpu_has_vmx_virtual_intr_...

...SECONDARY_EXEC_PAUSE_LOOP_EXITING | + SECONDARY_EXEC_ENABLE_INVPCID); if ( opt_vpid_enabled ) opt |= SECONDARY_EXEC_ENABLE_VPID; if ( opt_unrestricted_guest_enabled ) @@ -726,7 +727,8 @@ static int construct_vmcs(struct vcpu *v { v->arch.hvm_vmx.secondary_exec_control &= ~(SECONDARY_EXEC_ENABLE_EPT | - SECONDARY_EXEC_UNRESTRICTED_GUEST); + SECONDARY_EXEC_UNRESTRICTED_GUEST | + SECONDARY_EXEC_ENABLE_INVPCID); vmexit_ctl &= ~(VM_EXIT_SAVE_GUEST_PAT |...

This patch series is a reworking of a series developed by Mukesh Rathor at Oracle. The entirety of the design and development was done by him; I have only reworked, reorganized, and simplified things in a way that I think makes more sense. The vast majority of the credit for this effort therefore goes to him. This version is labelled v13 because it is based on his most recent series, v11.

From: Yang Zhang <yang.z.zhang@Intel.com> The following patches fix the issue that fail to boot L2 guest on APIC-v available machine. The main problem is that with APIC-v, virtual interrupt inject L1 is totally through APIC-v. But if virtual interrupt is arrived when L2 is running, L1 will detect interrupt through vmexit with reason external interrupt. If this happens, we should update

while doing "while xm migrate --live domU localhost;do sleep 1;done" I just got the crash shown below. And it can be reproduced. The guest has 2 vcpus and 512mb, it runs pvops 3.7.9 (XEN) ----[ Xen-4.3.26579-20130219.172714 x86_64 debug=n Not tainted ]---- (XEN) CPU: 14 (XEN) RIP: e008:[<ffff82c4c01dd197>] nvmx_vcpu_destroy+0xb7/0x150 (XEN) RFLAGS: 0000000000010282

This series of patches fix the mistake for debug exception(#DB), overflow exception(#OF) and INT3(#BP), INTn instruction emulation. Introduce new function vmx_inject_sw_exception() which deliver the software excetion, software interrupt and privileged software exception. Split hardware exception as a seperate function(old function vmx_inject_hw_exception()). Also Passed down intruction length

Changes from v1: - Define new struct hvm_trap to represent information of trap, include instruction length. - Renames hvm_inject_exception to hvm_inject_trap. Then define a couple of wrappers around that function for existing callers, so that their parameter lists actually *shrink*. This series of patches fix the mistake for debug exception(#DB), overflow exception(#OF) and INT3(#BP),

A character device for accessing (in user-space) pages that have been granted by other domains. Signed-off-by: Derek Murray <Derek.Murray@cl.cam.ac.uk> _______________________________________________ Xen-devel mailing list Xen-devel@lists.xensource.com http://lists.xensource.com/xen-devel

From: Zhang Xiantao <xiantao.zhang@intel.com> With virtual EPT support, L1 hyerpvisor can use EPT hardware for L2 guest''s memory virtualization. In this way, L2 guest''s performance can be improved sharply. According to our testing, some benchmarks can show > 5x performance gain. Signed-off-by: Zhang Xiantao <xiantao.zhang@intel.com> Zhang Xiantao (11):